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A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC with Dynamic Gm-R-Based Amplifier Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 2,Page: 322-332
Authors:  Jiang,Wenning;  Zhu,Yan;  Zhang,Minglei;  Chan,Chi Hang;  Martins,Rui Paulo
Favorite |  | TC[WOS]:3 TC[Scopus]:4 | Submit date:2021/03/09
Analog-to-digital converter (ADC)  Gm-R amplifier  pipelined-successive approximation register (SAR) ADC  residue amplifier (RA)  SAR  SAR-assisted pipelined ADC  temperature compensation  
A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3606-3616
Authors:  Zhu Y.;  Chan C.-H.;  Zheng Z.-H.;  Li C.;  Zhong J.-Y.;  Martins R.P.
Favorite |  | TC[WOS]:4 TC[Scopus]:4 | Submit date:2019/02/11
passive sharing  pipelined-SAR ADC  sampling front-end design  switch bootstrap technique  Time-interleaved ADC  
A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Conference paper
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Zheng, Zi-Hao;  Li, Cheng;  Zhong, Jian-Yu;  Martins, Rui P.
Favorite |  | TC[WOS]:4 TC[Scopus]:4 | Submit date:2018/10/30
Time-interleaved ADC  sampling front-end design  passive sharing  pipelined-SAR ADC  switch bootstrap technique  
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 5,Page: 1223-1234
Authors:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  Rui Paulo Martins
Favorite |  | TC[WOS]:19 TC[Scopus]:22 | Submit date:2019/02/11
Offset Calibration  Pipelined-successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Sar Logic  
A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique Conference paper
2012 Proceedings of the ESSCIRC (ESSCIRC), Bordeaux, France, 17-21 Sept. 2012
Authors:  Rui Wang;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Zhihua Wang;  Rui Paulo Martins
Favorite |  | TC[WOS]:0 TC[Scopus]:13 | Submit date:2019/02/11
Sar Adc  Pipelined  Digital Calibration  Op-amp Sharing  
A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC and self-embedded offset cancellation Journal article
IEEE Journal of Solid-State Circuits, 2012,Volume: 47,Issue: 11,Page: 2614-2626
Authors:  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite |  | TC[WOS]:21 TC[Scopus]:26 | Submit date:2018/10/30
Decoupled Flip-around Mdac  Offset-cancellation  Pipelined-sar Adc  Vdd -attenuator  
A time-efficient dither-injection scheme for pipelined SAR ADC Conference paper
Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Macau, China, 6-7 Oct. 2011
Authors:  Wang R.;  Chio U.-F.;  Chan C.-H.;  Ding L.;  Sin S.-W.;  Seng-Pan U.;  Wang Z.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2019/02/11
Digital Calibration  Dither Injection  Pipelined  Sar Adc  
An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications Conference paper
2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings, Athens, Greece, 12-15 Dec. 2010
Authors:  Yin G.;  Chio U.-F.;  Wei H.-G.;  Sin S.-W.;  U S.-P.;  Martins R.P.;  Wang Z.
Favorite |  | TC[WOS]:0 TC[Scopus]:2 | Submit date:2019/02/11
Bio-medical Applications  Pipelined  Sar Adc  Ultra-low Power