UM

Browse/Search Results:  1-10 of 17 Help

Selected(0)Clear Items/Page:    Sort:
A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 2,Page: 557-568
Authors:  Jiang,Wenning;  Zhu,Yan;  Chan,Chi Hang;  Murmann,Boris;  Martins,Rui Paulo
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2021/03/04
Analog-to-digital converter  background timing skew calibration  current integrating sampler  SAR ADC  time-interleaved ADC  timing skew  
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 3,Page: 693-705
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:3 | Submit date:2021/03/04
Analog-to-digital converter (ADC)  digital background calibration  split ADC  time-interleaved (TI) ADC  timing-skew mismatch  
A 5 GS/s 29 mW Interleaved SAR ADC with 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications Journal article
IEEE Access, 2020,Volume: 8,Page: 138944-138954
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/09
Analog-to-digital converter (ADC)  digital background calibration  digital-mixing  time-interleaved (TI) ADC  timing mismatch  
A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration Conference paper
Proceedings of the Custom Integrated Circuits Conference
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:3 | Submit date:2021/03/09
background mismatch calibration  SAR analog-to-digital converter (ADC)  split ADC  time-interleaved (TI) ADC  timing-skew calibration  
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2019/02/13
Bandwidth mismatches  split-digital to analog converter (DAC)  successive-approximation-register (SAR) analog-to-digital converter (ADC)  time-interleaved (TI)  variance based  window detector (WD)  
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11
reference interference  SAR ADC  time-interleaved scheme  two-step SAR conversion  
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Authors:  Jiang W.;  Zhu Y.;  Chan C.-H.;  Murmann B.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:3 | Submit date:2019/02/11
background calibration  current integrating sampler  Time-interleaved ADC  timing skew  
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018,Volume: 65,Issue: 11,Page: 1534-1538
Authors:  Wang, X. Shawn;  Jin, Xin;  Du, Jieqiong;  Li, Yilei;  Du, Yuan;  Wong, Chien-Heng;  Kuan, Yen-Cheng;  Chan, Chi-Hang;  Chang, Mau-Chung Frank
Favorite |  | TC[WOS]:3 TC[Scopus]:3 | Submit date:2019/01/17
Analog-to-digital converter (ADC)  virtual-ground sampling  SAR  time-interleaved  
A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3606-3616
Authors:  Zhu Y.;  Chan C.-H.;  Zheng Z.-H.;  Li C.;  Zhong J.-Y.;  Martins R.P.
Favorite |  | TC[WOS]:4 TC[Scopus]:4 | Submit date:2019/02/11
passive sharing  pipelined-SAR ADC  sampling front-end design  switch bootstrap technique  Time-interleaved ADC  
A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Conference paper
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Zheng, Zi-Hao;  Li, Cheng;  Zhong, Jian-Yu;  Martins, Rui P.
Favorite |  | TC[WOS]:4 TC[Scopus]:4 | Submit date:2018/10/30
Time-interleaved ADC  sampling front-end design  passive sharing  pipelined-SAR ADC  switch bootstrap technique