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A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3108-3112
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In;  Li, Qiang;  Martins, Rui P.
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analog phase-locked loop (PLL)  Area  charge-sharing integrator  CMOS  digital PLL  hybrid PLL  integer-N  integrator  jitter  ring oscillator  ultra-low power  
A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3093-3097
Authors:  Huang, Yunbo;  Chen, Yong;  Jiao, Hailong;  Mak, Pui In;  Martins, Rui P.
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CMOS  narrow pulse shielding  reference (REF) feedthrough suppression  sampling phase-locked loop (S-PLL)  T-shape switch  type-I  voltage-controlled oscillator (VCO)  
An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3143-3147
Authors:  Li, Jixuan;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In;  Martins, Rui P.
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Computation efficiency  convolutional neural network (CNN)  FPGA  object recognition  reconfigurability  
Adaptive Maximum Power Point Tracking with Model-Based Negative Feedback Control and Improved V-f Model Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3103-3107
Authors:  Wang, Yuanfei;  Huang, Mo;  Luo, Ping;  Lu, Yan;  Martins, Rui P.
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energy harvesting system~(EHS)  maximum input power point tracking (MIPPT)  maximum output power point tracking (MOPPT)  Model-based method  NFC-based MPPT  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
IEEE Journal of Solid-State Circuits, 2021,Volume: 56,Issue: 8,Page: 2375-2387
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
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Analog-to-digital converter (ADC)  data weighting average (DWA)  delta-sigma modulator (DSM)  digital bank filters  digital-to-analog converter (DAC)  discrete-time (DT)  dithering  dynamic element matching (DEM)  extrapolation  noise-coupling  time-domain analysis  time-interleaved (TI)  
A Time-Domain CMOS Temperature Sensor Using Gated Ring Oscillator with Linearity Optimization Conference paper
ISSCS 2021 - International Symposium on Signals, Circuits and Systems
Authors:  Liu, Yangyang;  Lei, Yu;  Law, Man Kay;  Veigas, Bruno;  Mak, Pui In;  Martins, Rui P.
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BJT  CMOS temperature sensor  Gated ring oscillator  Linearity optimization  Time domain  
A highly integrated 3-phase 4:1 Resonant switched-capacitor converter with parasitic loss reduction and fast pre-charge startup Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 7,Page: 2608-2612
Authors:  Wang, Chuang;  Lu, Yan;  Martins, Rui P.
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3-phase operation  DC-DC converter  highly-integrated  resonant switched-capacitor converter  
A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Zhang, Minglei;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
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Background  input independent  time domain ADC  time-interleaved ADC  timing skew calibration  
A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS Conference paper
Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Wang, Lin;  Mak, Pui In;  Maloberti, Franco;  Martins, Rui P.
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4-level pulse amplitude modulation (PAM-4)  Bang-bang clock and data recovery (BBCDR)  Charge pump (CP)  CMOS  Frequency detector (FD)  Half-rate  Negative (NNC) net current  Positive (PNC)  Reference less  Single loop  Zero (ZNC)  
A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 6,Page: 2307-2316
Authors:  Yang, Zunsong;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
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CMOS  current-reuse sampling phase detector (CRS-PD)  integrated jitter  loop filter (LF)  master-slave sampling filter (MSSF)  master-slave sampling phase detector (MSS-PD)  phase noise (PN)  Phase-locked loop (PLL)  reference spur  ring voltage-controlled oscillator (VCO)  type-I  type-II