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A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio Conference paper
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings
Authors:  Wei, Dong;  Wu, Tianxiang;  Ma, Shunli;  Chen, Yong;  Ren, Junyan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/12/08
5G new radio  CMOS  common gate  common source  fractional bandwidth (BW)  gain flatness  gm boosting  IEEE 802.11aj  Low-noise amplifier (LNA)  magnetically coupling resonator  noise factor  noise figure (NF)  transformer  
A sub-6g sp32t single-chip switch with nanosecond switching speed for 5g applications in 0.25 µm gaas technology Journal article
Electronics (Switzerland), 2021,Volume: 10,Issue: 12
Authors:  Wu, Tianxiang;  Wei, Jipeng;  Liu, Hongquan;  Ma, Shunli;  Chen, Yong;  Ren, Junyan
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2021/10/28
Gaas Process  Pseudomorphic High-electron-mobility Transistor (Phemt)  Single-pole 32-throw (Sp32t) Switch  Sub-6g  
A 120-150 GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm Psatfor Sub-THz Imaging System Journal article
IEEE Access, 2021,Volume: 9,Page: 74752-74762
Authors:  Zhang, Jincheng;  Wu, Tianxiang;  Nie, Lihe;  Ma, Shunli;  Chen, Yong;  Ren, Junyan
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2021/10/28
Cmos  D-band  Frequency Modulated Continuous Wave (Fmcw)  Imaging System  Power Amplifier (Pa)  Power Combining  Sub-terahertz (Sub-thz)  
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS Journal article
IEEE Access, 2021,Volume: 9,Page: 77545-77554
Authors:  Li, Manxin;  Yao, Yuting;  Hu, Biao;  Wei, Jipeng;  Chen, Yong;  Ma, Shunli;  Ye, Fan;  Ren, Junyan
Favorite |  | TC[WOS]:1 TC[Scopus]:0 | Submit date:2021/10/28
Asynchronous Logic  Cmos  Customized Unit Capacitor  Figure-of-merit (Fom)  Split-cdac  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017,Volume: 25,Issue: 3,Page: 1168-1172
Authors:  Dezhi Xing;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Fan Ye;  Junyan Ren;  Seng-Pan U;  Rui Paulo Martins
Favorite |  | TC[WOS]:8 TC[Scopus]:11 | Submit date:2019/02/11
Common Mode Variation  Partial Vcm-based Switching  Time-interleaved Successive ApproximaTion Register Analog-to-digital Converter (Ti Sar Adc)  
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial V-cm-Based Switching Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 3,Page: 1168-1172
Authors:  Xing, Dezhi;  Zhu, Yan;  Chan, Chi-Hang;  Sin, Sai-Weng;  Ye, Fan;  Ren, Junyan;  U, Seng-Pan;  Martins, Rui Paulo
Favorite |  | TC[WOS]:8 TC[Scopus]:11 | Submit date:2018/10/30
Common mode variation  partial V-cm-based switching  time-interleaved successive approximation register analog-to-digital converter (TI SAR ADC)