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A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Jiang,Dongyang;  Qi,Liang;  Sin,Sai Weng;  Maloberti,Franco;  Martins,R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/04
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 2,Page: 344-355
Authors:  Qi,Liang;  Jain,Ankesh;  Jiang,Dongyang;  Sin,Sai Weng;  Martins,Rui P.;  Ortmanns,Maurits
Favorite |  | TC[WOS]:3 TC[Scopus]:4 | Submit date:2021/03/09
Analog-to-digital converter (ADC)  continuous time (CT)  digital-to-analog converter (DAC) linearization  excess loop delay (ELD) compensation  filter  finite-impulse response (FIR)  multibit quantization  noise coupling (NC)  sturdy multistage noise-shaping (SMASH)  successive-approximation register (SAR)  
Multibit sturdy mash δσ modulator with error-shaped segmented dacs for wideband low-power applications Conference paper
Proceedings of International Conference on ASIC
Authors:  Qi,Liang;  Sin,Sai Weng;  Martins,Rui Paulo
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
20.5 A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Qi,Liang;  Jain,Ankesh;  Jiang,Dongyang;  Sin,Sai Weng;  Martins,Rui P.;  Ortmanns,Maurits
Favorite |  | TC[WOS]:0 TC[Scopus]:4 | Submit date:2021/03/09