UM

Browse/Search Results:  1-9 of 9 Help

Selected(0)Clear Items/Page:    Sort:
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC Journal article
IEEE Journal of Solid-State Circuits, 2020
Authors:  Song,Yan;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
Analog-to-digital converter (ADC)  Calibration  Capacitors  Gain  noise-shaping (NS)  offset calibration  Pipelines  Registers  successive approximation register (SAR)-assisted pipeline  System-on-chip  time interleaving.  Transfer functions  
Background Offset Calibration for Comparator Based on Temperature Drift Profile Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 10,Page: 1648-1652
Authors:  Li,Xiaochao;  Chan,Chi Hang;  Zhang,Qi;  Zhu,Yan;  Martins,R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:2 | Submit date:2021/03/09
background self-calibration  Offset drift  preamplifier comparator  
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite |  | TC[WOS]:20 TC[Scopus]:27 | Submit date:2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 1,Page: 354-363
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Pan, Seng U.;  Martins, Rui Paulo
Favorite |  | TC[WOS]:8 TC[Scopus]:8 | Submit date:2018/10/30
Offset Calibration  Partial Interleaving (Pi)  Pipelined-sar  Stage-gain Error Calibration  
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 5,Page: 1223-1234
Authors:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  Rui Paulo Martins
Favorite |  | TC[WOS]:20 TC[Scopus]:24 | Submit date:2019/02/11
Offset Calibration  Pipelined-successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Sar Logic  
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 2,Page: 365-377
Authors:  Chi-Hang Chan;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan (Ben) U;  Rui Paulo Martins
Favorite |  | TC[WOS]:17 TC[Scopus]:22 | Submit date:2019/02/11
Analog-to-digital Conversion  Interleaving  Interpolation  Multibit/cycle Sar  Offset Calibration  
A Noise-Insensitive Offset Calibration Technique for Time Interleaved SAR ADC Conference paper
Proc. IEEE International Symposium on Circuits and Systems – LASCAS 2010, Iguaçu Falls, Brazil, February 2010
Authors:  Li Ding;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/03/28
Digital Offset Calibration  Noise Averaging  Time Interleaved Adc  
Parasitic calibration by two-step ratio approaching techinque for split capacitor array SAR ADCs Conference paper
2009 International SoC Design Conference, ISOCC 2009, Busan, South Korea, 22-24 Nov. 2009
Authors:  Wong S.-S.;  Zhu Y.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite |  | TC[WOS]:5 TC[Scopus]:9 | Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Offset Calibration  Parasitic Calibration  Split Capacitor Array  Sucessive Approximation Register (Sar)  
A voltage-controlled capacitance offset calibration technique for high resolution dynamic comparator Conference paper
2009 International SoC Design Conference, ISOCC 2009, Busan, South Korea, 22-24 Nov. 2009
Authors:  Chan C.-H.;  Zhu Y.;  Chio U.-F.;  Sin S.-W.;  U S.P.;  Martins R.P.
Favorite |  | TC[WOS]:10 TC[Scopus]:16 | Submit date:2019/02/11
Dynamic Comparator  Offset Calibration