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A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Jiang,Dongyang;  Qi,Liang;  Sin,Sai Weng;  Maloberti,Franco;  Martins,R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/04
A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator Conference paper
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Authors:  Liang,Junhao;  Sin,Sai Weng;  Seng-Pan,U.;  Maloberti,Franco;  Martins,R. P.;  Jiang,Hanjun
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
CT sigma delta AD converter  ECG  high impedance  non-invertering integrator  Programmable integrator  
A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS Conference paper
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Authors:  Wang,Biao;  Sin,Sai Weng;  Seng-Pan,U.;  Maloberti,Franco;  Martins,R. P.
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Data Weighted Averaging  Linear-exponential  Multi-Bit Incremental ADC  Positive Feedback  
Background Offset Calibration for Comparator Based on Temperature Drift Profile Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 10,Page: 1648-1652
Authors:  Li,Xiaochao;  Chan,Chi Hang;  Zhang,Qi;  Zhu,Yan;  Martins,R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/09
background self-calibration  Offset drift  preamplifier comparator  
A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR with Fully-Digital Timing-Skew Calibration Based on Digital-Mixing Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:4 | Submit date:2021/03/09
A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration Conference paper
Proceedings of the Custom Integrated Circuits Conference
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:3 | Submit date:2021/03/09
background mismatch calibration  SAR analog-to-digital converter (ADC)  split ADC  time-interleaved (TI) ADC  timing-skew calibration  
A Calibration Scheme for Stability of Self-biased Ring Amplifier Conference paper
Authors:  Yan, Rongshen;  Chan, Chi-Hang;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, R. P.;  Wang, ZH;  Xie, WH
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2018/10/30
Calibration  Self-biased Ring Amplifier  PVT Variations  Oscillation Detection  Programmable Resistor  
A 0.4V 4.8 mu W 16MHz CMOS Crystal Oscillator Achieving 74-Fold Startup-Time Reduction Using Momentary Detuning Conference paper
Authors:  Lei, Ka-Meng;  Mak, Pui-In;  Martins, R. P.;  IEEE
Favorite |  | TC[WOS]:1 TC[Scopus]:0 | Submit date:2018/10/30
CMOS  crystal oscillator  fast startup  low-voltage  low-power  ultra-low-power  
Capacitive floating level shifter: Modeling and design Conference paper
IEEE Region 10 Annual International Conference, Proceedings/TENCON
Authors:  Zheng,Wen Ming;  Lam,Chi Seng;  Sin,Sai Weng;  Lu,Yan;  Wong,Man Chung;  Seng-Pan,U.;  Martins,R. P.
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DC-DC converter  floating level shifter  fully-integrated  level shifter  switched-capacitor  
Linearity analysis on a series-split capacitor array for high-speed SAR ADCs Journal article
VLSI Design, 2010,Volume: 2010
Authors:  Zhu,Yan;  Chio,U. Fat;  Wei,He Gong;  Sin,Sai Weng;  Seng-Pan,U.;  Martins,R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:4 | Submit date:2021/03/09