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A 0.024-mm245.4-GHz-Bandwidth Unity-Gain Output Driver with SDD22<-10dB up to 35 GHz Conference paper
Midwest Symposium on Circuits and Systems
Authors:  Chen,Yong;  Mak,Pui In;  Chye Boon,Chirn;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/04
A 0.096-mm2 1-20-GHz triple-path noise- canceling common-gate common-source LNA with dual complementary pMOS-nMOS configuration Journal article
IEEE Transactions on Microwave Theory and Techniques, 2020,Volume: 68,Issue: 1,Page: 144-159
Authors:  Yu,Haohong;  Chen,Yong;  Boon,Chirn Chye;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:4 TC[Scopus]:6 | Submit date:2021/03/09
CMOS  common gate (CG)  common source (CS)  input third-order intercept point (IIP3)  noise figure (NF)  partial distortion canceling  pMOS-nMOS configuration  resistive feedback  triple-path and dual-path noise canceling (NC)  wideband input matching  wideband low-noise amplifier (LNA)  
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique Conference paper
Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption
Authors:  Kong,Lingshan;  Chen,Yong;  Yu,Haohong;  Pan,Quan;  Boon,Chirn Chye;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/09
bandwidth (BW)  CMOS  high-speed transceiver  negative capacitance  peak-to-peak jitter  pseudo-current steering  variable-gain amplifier (VGA)  wide-tuning gain control  
A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 10,Page: 3991-4004
Authors:  Chen,Yong;  Mak,Pui In;  Yang,Zunsong;  Boon,Chirn Chye;  Martins,Rui P.
Favorite |  | TC[WOS]:5 TC[Scopus]:5 | Submit date:2021/03/09
active inductor (AI)  bandwidth (BW) extension  CMOS  current reuse  current-mode logic (CML)  current-mode transmitter  data-dependent jitter (DDJ)  figure-of-merit (FOM)  flip-flop (FF)  Fractional de-emphasis (DE)  hybrid delay line  latch  pulse-width-modulated (PWM)  unit interval (UI)  
A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications Journal article
IEEE SENSORS JOURNAL, 2018,Volume: 18,Issue: 11,Page: 4553-4560
Authors:  Sunny, Sharma;  Chen, Yong;  Boon, Chirn Chye
Favorite |  | TC[WOS]:3 TC[Scopus]:4 | Submit date:2018/10/30
1.5-bit/cycle  ADC  capacitive digital-to-analog converter (CDAC)  CMOS  error correction  low power  medical imaging  redundancy  SAR  successive approximation register  
A 0.013-mm(2) 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 3,Page: 599-603
Authors:  Balachandran, Arya;  Chen, Yong;  Boon, Chirn Chye
Favorite |  | TC[WOS]:2 TC[Scopus]:4 | Submit date:2018/10/30
Channel loss  CMOS equalizer  continuous-time linear equalizer (CTLE)  figure of merit (FOM)  inductorless  intersymbol interference (ISI)  low-frequency equalization (LFEQ)  
0.058 mm(2) 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss Journal article
ELECTRONICS LETTERS, 2018,Volume: 54,Issue: 2
Authors:  Balachandran, Arya;  Chen, Yong;  Choi, Pilsoon;  Boon, Chirn Chye
Favorite |  | TC[WOS]:2 TC[Scopus]:4 | Submit date:2018/10/30
equalisers  circuit feedback  analogue circuits  random sequences  binary sequences  CMOS analogue integrated circuits  inductorless analogue equaliser  low-frequency equalisation compensation  LFEQ  low-frequency channel loss  active feedback topology  negative capacitance circuit  data jitter  pseudorandom binary sequence  CMOS technology  loss 15 dB  bit rate 13 Gbit  s  size 65 nm  voltage 1  2 V  
A 27-Gb/s Time-Interleaved Duobinary Transmitter Achieving 1.44-mW/Gb/s FOM in 65-nm CMOS Journal article
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2017,Volume: 27,Issue: 9,Page: 839-841
Authors:  Chen, Yong;  Mak, Pui-In;  Boon, Chirn Chye;  Martins, Rui P.
Favorite |  | TC[WOS]:6 TC[Scopus]:6 | Submit date:2018/10/30
Cmos  Duobinary  Figure-of-merit (Fom)  Flip-flop (Ff)  Latch  Multiplexer (Mux)  Selector  Time-interleaved