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An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC Conference paper
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), Venezia Lido, ITALY, 22-26 Sept. 2014
Authors:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  R.P.Martins
Favorite |  | TC[WOS]:12 TC[Scopus]:13 | Submit date:2019/02/11
Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S pipelined-SAR ADC Conference paper
2012 IEEE Asian Solid State Circuits Conference (A-SSCC), Kobe, JAPAN, NOV 12-14, 2012
Authors:  Jianyu Zhong;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  Rui P. Martins
Favorite |  | TC[WOS]:5 TC[Scopus]:6 | Submit date:2019/02/11
Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects Journal article
IEEE Transactions on Instrumentation and Measurement, 2004,Volume: 53,Issue: 4,Page: 1279-1288
Authors:  U S.-P.;  Sin S.-W.;  Martins R.P.
Favorite |  | TC[WOS]:10 TC[Scopus]:9 | Submit date:2019/02/11
Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems, BANGKOK, THAILAND, MAY 25-28, 2003
Authors:  Sin S.-W.;  Martins R.P.;  Franca J.E.;  Seng-Pan U
Favorite |  | TC[WOS]:1 TC[Scopus]:0 | Submit date:2019/02/11
Spectra analysis of nonuniformly holding signals for time-interleaved systems with timing mismatches Conference paper
Conference Record - IEEE Instrumentation and Measurement Technology Conference, VAIL, CO, MAY 20-22, 2003
Authors:  Sin S.-W.;  Martins R.P.;  U, SP
Favorite |  | TC[WOS]:1 TC[Scopus]:0 | Submit date:2019/02/11
Signal Analysis  Timing  Signal Processing  Frequency  Clocks  Signal Sampling  Jitter  Silicon Compounds  Closed-form Solution  Error Analysis  
Offset- and gain-compensated and mismatch-free SC delay circuit with flexible implementation Journal article
Electronics Letters, 1999,Volume: 35,Issue: 3,Page: 188-189
Authors:  Seng-Pan U.;  Martins R.P.;  Franca J.E.
Favorite |  | TC[WOS]:3 TC[Scopus]:0 | Submit date:2019/02/11
Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity Journal article
Proceedings - IEEE International Symposium on Circuits and Systems, 1999,Volume: 2
Authors:  U Seng-Pan;  Martins R.P.;  Franca J.E.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11