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| A 5 GS/s 29 mW Interleaved SAR ADC with 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications Journal article
IEEE Access, 2020,Volume: 8,Page: 138944-138954
Authors: Guo，Mingqiang; Mao，Jiaji; Sin，Sai Weng; Wei，Hegong; Martins，Rui P.
  Favorite | | TC[WOS]:0 TC[Scopus]:1 | Submit date：2021/03/09
Analog-to-digital converter (ADC) digital background calibration digital-mixing time-interleaved (TI) ADC timing mismatch |
| Nano-Watt Class Energy-Efficient Capacitive Sensor Interface with On-Chip Temperature Drift Compensation Journal article
IEEE Sensors Journal, 2018,Volume: 18,Issue: 7,Page: 2870-2882
Authors: Zhang T.-T.; Law M.-K. ; Mak P.-I.; Vai M.-I.; Martins R.P.
Favorite | | TC[WOS]:5 TC[Scopus]:6 | Submit date：2019/02/11
Capacitive Sensor Interface Energy Efficiency High Accuracy Mismatch Errors Pressure Sensor Temperature Compensation Two-step Incremental-adc Ultra-low Power |
| Comparison of different Tc-99m-MAA imaging protocols for Y-90 SIRT treatment planning Conference paper
J Nucl Med, Atlanta, GA, USA, October 21 – 28, 2017
Authors: Mingren Feng; Tiantian Li; Nien-Yun Wu; Greta Mok
Favorite | | TC[WOS]:0 TC[Scopus]:0 | Submit date：2019/01/28 |
| Distributed hybrid power state estimation under PMU sampling phase errors Journal article
IEEE Transactions on Signal Processing, 2014,Volume: 62,Issue: 16,Page: 4052-4063
Authors: Du J.; Ma S.; Wu Y.-C.; Poor H.V.
Favorite | | TC[WOS]:20 TC[Scopus]:23 | Submit date：2019/02/14
Phase Mismatch Pmu Scada State Estimation |
| An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC Conference paper
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), Venezia Lido, ITALY, 22-26 Sept. 2014
Authors: Yan Zhu; Chi-Hang Chan; Seng-Pan U; R.P.Martins
Favorite | | TC[WOS]:12 TC[Scopus]:13 | Submit date：2019/02/11 |
| As Good as Married? A Model of Premarital Cohabitation and Learning Journal article
JOURNAL OF MATHEMATICAL SOCIOLOGY, 2013,Volume: 37,Issue: 3,Page: 133-158
Authors: Padma Rao Sahib; Xinhua Gu
Favorite | | TC[WOS]:4 TC[Scopus]:3 | Submit date：2019/11/14
Bayesian Learning Imperfect Information Marriage Premarital Cohabitation Two-sided Search-matching |
| Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S pipelined-SAR ADC Conference paper
2012 IEEE Asian Solid State Circuits Conference (A-SSCC), Kobe, JAPAN, NOV 12-14, 2012
Authors: Jianyu Zhong; Yan Zhu; Sai-Weng Sin; Seng-Pan U; Rui P. Martins
Favorite | | TC[WOS]:5 TC[Scopus]:6 | Submit date：2019/02/11 |
| Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects Journal article
IEEE Transactions on Instrumentation and Measurement, 2004,Volume: 53,Issue: 4,Page: 1279-1288
Authors: U S.-P.; Sin S.-W.; Martins R.P.
Favorite | | TC[WOS]:10 TC[Scopus]:9 | Submit date：2019/02/11 |
| Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems, BANGKOK, THAILAND, MAY 25-28, 2003
Authors: Sin S.-W.; Martins R.P.; Franca J.E.; Seng-Pan U
Favorite | | TC[WOS]:1 TC[Scopus]:0 | Submit date：2019/02/11 |
| Spectra analysis of nonuniformly holding signals for time-interleaved systems with timing mismatches Conference paper
Conference Record - IEEE Instrumentation and Measurement Technology Conference, VAIL, CO, MAY 20-22, 2003
Authors: Sin S.-W.; Martins R.P.; U, SP
Favorite | | TC[WOS]:1 TC[Scopus]:0 | Submit date：2019/02/11
Signal Analysis Timing Signal Processing Frequency Clocks Signal Sampling Jitter Silicon Compounds Closed-form Solution Error Analysis |
