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A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 2,Page: 557-568
Authors:  Jiang,Wenning;  Zhu,Yan;  Chan,Chi Hang;  Murmann,Boris;  Martins,Rui Paulo
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2021/03/04
Analog-to-digital converter  background timing skew calibration  current integrating sampler  SAR ADC  time-interleaved ADC  timing skew  
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC with <1.5-ps Uncalibrated Quantization Steps Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 12,Page: 3225-3235
Authors:  Zhang,Minglei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/04
Analog-to-digital converter (ADC)  and temperature (PVT) robustness  high-speed ADC  metastability  process  supply voltage  time interpolation  time residue  time-domain ADC  time-to-digital converter (TDC)  
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 3,Page: 693-705
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:4 | Submit date:2021/03/04
Analog-to-digital converter (ADC)  digital background calibration  split ADC  time-interleaved (TI) ADC  timing-skew mismatch  
A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Zhang,Minglei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:4 | Submit date:2021/03/04
A 5 GS/s 29 mW Interleaved SAR ADC with 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications Journal article
IEEE Access, 2020,Volume: 8,Page: 138944-138954
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/09
Analog-to-digital converter (ADC)  digital background calibration  digital-mixing  time-interleaved (TI) ADC  timing mismatch  
A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR with Fully-Digital Timing-Skew Calibration Based on Digital-Mixing Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:4 | Submit date:2021/03/09
A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration Conference paper
Proceedings of the Custom Integrated Circuits Conference
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:3 | Submit date:2021/03/09
background mismatch calibration  SAR analog-to-digital converter (ADC)  split ADC  time-interleaved (TI) ADC  timing-skew calibration  
3.2 A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Jiang,Wenning;  Zhu,Yan;  Zhang,Minglei;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:10 | Submit date:2021/03/09
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11
reference interference  SAR ADC  time-interleaved scheme  two-step SAR conversion  
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2019/02/13
Bandwidth mismatches  split-digital to analog converter (DAC)  successive-approximation-register (SAR) analog-to-digital converter (ADC)  time-interleaved (TI)  variance based  window detector (WD)