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An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4thNyquist Zone in 1GS/s ADC Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Wei, Lai;  Zheng, Zihao;  Markulic, Nereo;  Lagos, Jorge;  Martens, Ewout;  Zhu, Yan;  Chan, Chi Hang;  Craninckx, Jan;  Martins, Rui Paulo
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Background calibration  nonlinearity  pipelined ADC  split-SAR ADC  
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS Journal article
IEEE Access, 2021,Volume: 9,Page: 77545-77554
Authors:  Li, Manxin;  Yao, Yuting;  Hu, Biao;  Wei, Jipeng;  Chen, Yong;  Ma, Shunli;  Ye, Fan;  Ren, Junyan
Favorite |  | TC[WOS]:1 TC[Scopus]:0 | Submit date:2021/10/28
Asynchronous Logic  Cmos  Customized Unit Capacitor  Figure-of-merit (Fom)  Split-cdac  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  
A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture Conference paper
Proceedings of the Custom Integrated Circuits Conference
Authors:  Zhang, Yanbo;  Zhang, Jin;  Liu, Shubin;  Zhu, Zhangming;  Zhu, Yan;  Chan, Chi Hang;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 3,Page: 693-705
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Favorite |  | TC[WOS]:10 TC[Scopus]:13 | Submit date:2021/03/04
Analog-to-digital Converter (Adc)  Digital Background Calibration  Split Adc  Time-interleaved (Ti) Adc  Timing-skew Mismatch  
A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration Conference paper
Proceedings of the Custom Integrated Circuits Conference
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:4 | Submit date:2021/03/09
background mismatch calibration  SAR analog-to-digital converter (ADC)  split ADC  time-interleaved (TI) ADC  timing-skew calibration  
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2019/02/13
Bandwidth mismatches  split-digital to analog converter (DAC)  successive-approximation-register (SAR) analog-to-digital converter (ADC)  time-interleaved (TI)  variance based  window detector (WD)  
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016,Volume: 24,Issue: 7,Page: 2603-2607
Authors:  Jianwei Liu;  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo da Silva Martins
Favorite |  | TC[WOS]:8 TC[Scopus]:9 | Submit date:2019/02/14
Background Linearity Calibration  Splitdigital- To-analog Converter (Dac)  Successive Approximation Register (Sar) Adc  Uniform Quantization Theory (Uqt)  
Split-SAR ADCs: Improved linearity with power and speed optimization Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014,Volume: 22,Issue: 2,Page: 372-383
Authors:  Yan Zhu;  Chi-Hang Chan;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo Martins;  Franco Maloberti
Favorite |  | TC[WOS]:37 TC[Scopus]:43 | Submit date:2018/10/30
Linearity Analysis  Linearity Calibration  Sar Adcs  Split Dac  Vcm-based Switching  
Parasitics nonlinearity cancellation technique for split DAC architecture by using capacitive charge-pump Conference paper
Midwest Symposium on Circuits and Systems, Seattle, WA, AUG 01-04, 2010
Authors:  Zhu Y.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:9 | Submit date:2019/02/11
A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs Conference paper
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 30 May-2 June 2010
Authors:  Zhu Y.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:11 | Submit date:2019/02/11