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A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3108-3112
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In;  Li, Qiang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
analog phase-locked loop (PLL)  Area  charge-sharing integrator  CMOS  digital PLL  hybrid PLL  integer-N  integrator  jitter  ring oscillator  ultra-low power  
A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 6,Page: 2307-2316
Authors:  Yang, Zunsong;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
CMOS  current-reuse sampling phase detector (CRS-PD)  integrated jitter  loop filter (LF)  master-slave sampling filter (MSSF)  master-slave sampling phase detector (MSS-PD)  phase noise (PN)  Phase-locked loop (PLL)  reference spur  ring voltage-controlled oscillator (VCO)  type-I  type-II  
A 0.003-mm2 440fsRMS-Jitter and-64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Conference paper
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macau, 4-6 Nov. 2019
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:5 | Submit date:2021/03/09
Phase Detector  Phase Locked Loop (Pll)  Reference Spur  Ring Voltage-controlled Oscillator (Vco)  Rms Jitter  
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 9,Page: 3307-3316
Authors:  Un,Ka Fai;  Qi,Gengzhen;  Yin,Jun;  Yang,Shiheng;  Yu,Shupeng;  Ieong,Chio In;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:3 | Submit date:2021/03/09
Bang-bang  Digital Phase-locked Loop (Dpll)  Digital-to-time Converter (Dtc)  Gain Calibration  Ring Vco  Ultra-fast Settling  Ultra-low-power (Ulp)  Voltage-controlled Oscillator (Vco)  
A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 2,Page: 157-161
Authors:  Jiang T.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite |  | TC[WOS]:5 TC[Scopus]:4 | Submit date:2019/02/14
Bootstrap (Bt)  Low Voltage  Non-overlapping Clock  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:  Yang S.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite |  | TC[WOS]:12 TC[Scopus]:14 | Submit date:2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
Design Considerations of Distributed and Centralized Switched-Capacitor Converters for Power Supply On-Chip Journal article
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, 2018,Volume: 6,Issue: 2,Page: 515-525
Authors:  Lu, Yan;  Jiang, Junmin;  Ki, Wing-Hung
Favorite |  | TC[WOS]:9 TC[Scopus]:10 | Submit date:2018/10/30
Active-matrix Light-emitting Diode (Amled)  Amplifier  Charge Pump  Converter Ring  Dc-dc Converter  Digital Control  Dynamic Voltage Scaling (Dvs)  Fully Integrated Voltage Regulator (Fivr)  Hybrid Converter  Low-dropout Regulator (Ldo)  Multilevel  Multiphase  Resonant Converter  Switched-capacitor (Sc) Power Converter  Voltage-controlled Oscillator (Vco)  
A 0.18-V 382-mu W Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 6,Page: 1618-1627
Authors:  Yi, Haidong;  Yu, Wei-Han;  Mak, Pui-In;  Yin, Jun;  Martins, Rui P.
Favorite |  | TC[WOS]:27 TC[Scopus]:30 | Submit date:2018/10/30
Bandgap Reference (Bgr)  Bluetooth Low Energy (Ble)  Charge Pump (Cp)  Class-d Voltage-controlled Oscillator (Vco)  Cmos  Energy Harvesting  Low-noise Amplifier (Lna)  Micropower Manager (Mu Pm)  Power-gating  Receiver (Rx)  Ultra-low Power (Ulp)  Ultra-low Voltage (Ulv)  
A 0.18-V 382-μ W Bluetooth Low-Energy Receiver Front-End with 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2018,Volume: 53,Issue: 6,Page: 1618-1627
Authors:  Yi H.;  Yu W.-H.;  Mak P.-I.;  Yin J.;  Martins R.P.
Favorite |  | TC[WOS]:27 TC[Scopus]:30 | Submit date:2019/02/11
Bandgap reference (BGR)  Bluetooth low energy (BLE)  charge pump (CP)  class-D voltage-controlled oscillator (VCO)  CMOS  energy harvesting  low-noise amplifier (LNA)  micropower manager (μPM)  power-gating  receiver (RX)  ultra-low power (ULP)  ultra-low voltage (ULV)  
A 0.0056mm2all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrmsJitter and -249dB FOM Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, United states, 2 11, 2018 - 2 15, 2018
Authors:  Yang, Shiheng;  Yin, Jun;  Mak, Pui-In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:15 | Submit date:2018/11/06