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A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3108-3112
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In;  Li, Qiang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
analog phase-locked loop (PLL)  Area  charge-sharing integrator  CMOS  digital PLL  hybrid PLL  integer-N  integrator  jitter  ring oscillator  ultra-low power  
A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3093-3097
Authors:  Huang, Yunbo;  Chen, Yong;  Jiao, Hailong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2021/09/20
Cmos  Narrow Pulse Shielding  Reference (Ref) Feedthrough Suppression  Sampling Phase-locked Loop (S-pll)  T-shape Switch  Type-i  Voltage-controlled Oscillator (Vco)  
A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 6,Page: 2307-2316
Authors:  Yang, Zunsong;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
CMOS  current-reuse sampling phase detector (CRS-PD)  integrated jitter  loop filter (LF)  master-slave sampling filter (MSSF)  master-slave sampling phase detector (MSS-PD)  phase noise (PN)  Phase-locked loop (PLL)  reference spur  ring voltage-controlled oscillator (VCO)  type-I  type-II  
A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 3753-3763
Authors:  Yang,Xiaofeng;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui Paulo
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2021/03/04
calibration-free  discrete-time  gain tracking  Jitter  open-loop  phase noise cancellation (PNC)  phase-locked loop (PLL)  PVT  reference spur  ring voltage-controlled oscillator (RVCO)  
A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM Journal article
IEEE Solid-State Circuits Letters, 2020,Volume: 3,Page: 494-497
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/09
Cmos  In-band Phase Noise (Pn)  Narrow-pulse-sampling (Nps)  Phase-locked Loop (Pll)  Reference (Ref) Spur  T-shape Switch  Type-i  Voltage-controlled Oscillator (Vco)  
A 0.003-mm2 440fsRMS-Jitter and-64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Conference paper
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macau, 4-6 Nov. 2019
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:5 | Submit date:2021/03/09
Phase Detector  Phase Locked Loop (Pll)  Reference Spur  Ring Voltage-controlled Oscillator (Vco)  Rms Jitter  
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector Journal article
IEEE Access, 2019,Volume: 8,Page: 2222-2232
Authors:  Yang,Zunsong;  Chen,Yong;  Yang,Shiheng;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:5 TC[Scopus]:4 | Submit date:2021/03/09
Cmos  Divider-by-4  Dual Loop  Dynamic Latch  Figure-of-merit (Fom)  Frequency Detector (Fd)  Millimeter (Mm)-wave  Phase Detector (Pd)  Phase-locked Loop (Pll)  Voltage-controlled Oscillator (Vco)  Voltage-to-current Converter (Vic)  
A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 5,Page: 1351-1362
Authors:  Yang, Shiheng;  Yin, Jun;  Yi, Haidong;  Yu, Wei Han;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:16 TC[Scopus]:19 | Submit date:2021/10/28
Bluetooth Low Energy (Ble)  Cmos  Energy Harvesting  Master-slave Sampling Filter (Mssf)  Micropower Manager (Μpm)  Phase-locked Loop (Pll)  Power Amplifier (Pa)  Power Gating  Transmitter (Tx)  Ultralow-voltage (Ulv)  Voltage-controlled Oscillator (Vco)  
16.3 A -246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation over PVT Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Yang,Xiaofeng;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:6 | Submit date:2021/03/09
16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur Conference paper
2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, USA, 17-21 Feb. 2019
Authors:  Zunsong Yang;  Yong Chen;  Shiheng Yang;  Pui-In Mak;  Rui P. Martins
Favorite |  | TC[WOS]:0 TC[Scopus]:26 | Submit date:2019/03/13