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An Auxiliary-Channel-Sharing Background Distortion and Gain CalibrationAchieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC Conference paper
Proceeding of 2021 Symposium on VLSI
Authors:  Wei, L.;  Zheng, Z.;  Markulic, N.;  Lagos, J.;  Martens, E.;  Zhu, Y.;  Chan, C. H.;  Craninckx, J.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Background calibration  nonlinearity  pipelined ADC  split-SAR ADC  
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4thNyquist Zone in 1GS/s ADC Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Wei, Lai;  Zheng, Zihao;  Markulic, Nereo;  Lagos, Jorge;  Martens, Ewout;  Zhu, Yan;  Chan, Chi Hang;  Craninckx, Jan;  Martins, Rui Paulo
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Background calibration  nonlinearity  pipelined ADC  split-SAR ADC  
27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, ELECTR NETWORK, FEB 13-22, 2021
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Chan, Chi Hang;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier Journal article
IEEE Journal of Solid-State Circuits, 2021
Authors:  Zheng, Zihao;  Wei, Lai;  Lagos, Jorge;  Martens, Ewout;  Zhu, Yan;  Chan, Chi Hang;  Craninckx, Jan;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Analog-to-digital conversion  calibration  Calibration  dynamic amplifier (DA)  Hardware  Linearity  linearization technique  Pipeline processing  pipelined analog-to-digital converter (ADC).  Quantization (signal)  Signal resolution  System-on-chip  
LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter with Ripple Calibration Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 12,Page: 4174-4186
Authors:  Wang,Hanyu;  Sin,Sai Weng;  Lam,Chi Seng;  Maloberti,Franco;  Martins,Rui Paulo
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2021/03/04
Power Management  Switching-mode Power Converters  Boost Dc-dc Converters  Analog-to-digital Converters (Adcs)  Pipelined Adc  Ripple Calibration  
An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2020,Volume: 67,Issue: 7,Page: 1174-1178
Authors:  Zhang, Jin;  Ren, Xiaoqian;  Liu, Shubin;  Chan, Chi Hang;  Zhu, Zhangming
Favorite |  | TC[WOS]:2 TC[Scopus]:4 | Submit date:2021/12/06
Analog-to-digital Converter (Adc)  Full Dynamic Adc  Pipelined Successive-approximation-register (Sar)  Pvt-stabilized Dynamic Amplification  Reused Comparator  
Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020,Volume: 28,Issue: 4,Page: 1074-1078
Authors:  Sun, Jie;  Zhang, Minglei;  Qiu, Lei;  Wu, Jianhui;  Liu, Weiqiang
Favorite |  | TC[WOS]:5 TC[Scopus]:6 | Submit date:2021/10/28
Background Calibration  Bit Weight  Dither Injection  Pipelined Sar Adc  Residue Increment  
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation Conference paper
2020 IEEE International Solid- State Circuits Conference - (ISSCC)
Authors:   Zheng, Z.;  Wei, W.;  Lagos, J.;  Martens, E.;  Zhu, Y.;  Chan, C. H.;  Craninckx, J.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
amplifiers  analogue-digital conversion  calibration  interpolation  dynamic pipelined ADC  dynamic pipelined architecture  linearized dynamic amplifier  post-amplification residue generation scheme  residue amplification  complex residue-transferring realization  residue amplifier  power consumption  SAR ADC  calibration complexity  aggressive interpolation factor  flash ADC  mm-wave 5G receivers  ADC-based serial links  power 5.5 mW  Calibration  Quantization (signal)  Clocks  System-on-chip  Interpolation  Prototype  
A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, FEB 16-20, 2020
Authors:  Zheng,Zihao;  Wei,Lai;  Lagos,Jorge;  Martens,Ewout;  Zhu,Yan;  Chan,Chi Hang;  Craninckx,Jan;  Martins,Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:5 | Submit date:2021/03/04
A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC with Dynamic Gm-R-Based Amplifier Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 2,Page: 322-332
Authors:  Jiang,Wenning;  Zhu,Yan;  Zhang,Minglei;  Chan,Chi Hang;  Martins,Rui Paulo
Favorite |  | TC[WOS]:9 TC[Scopus]:9 | Submit date:2021/03/09
Analog-to-digital Converter (Adc)  Gm-r Amplifier  Pipelined-successive Approximation Register (Sar) Adc  Residue Amplifier (Ra)  Sar  Sar-assisted Pipelined Adc  Temperature Compensation