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A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
IEEE Journal of Solid-State Circuits, 2021,Volume: 56,Issue: 8,Page: 2375-2387
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Analog-to-digital converter (ADC)  data weighting average (DWA)  delta-sigma modulator (DSM)  digital bank filters  digital-to-analog converter (DAC)  discrete-time (DT)  dithering  dynamic element matching (DEM)  extrapolation  noise-coupling  time-domain analysis  time-interleaved (TI)  
Discrete-time mash delta-sigma modulator with second-order digital noise coupling for wideband high-resolution applications Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems
Authors:  Qin, Xinyu;  Zhang, Jingying;  Qi, Liang;  Sin, Sai Weng;  Martins, Rui P.;  Wang, Guoxing
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Digital noise coupling  Multistage noise shaping (MASH)  Noise leakage  Wideband high-resolution applications  ΔΣ modulator (DSM)  
A 0.082mm224.5-to-28.3GHz Multi-LC-Tank Fully-Differential VCO Using Two Separate Single-Turn Inductors and a 1D-Tuning Capacitor Achieving 189.4dBc/Hz FOM and 200±50kHz 1/f3PN Corner Conference paper
Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, Los Angeles, CA, USA, 4-6 Aug. 2020
Authors:  Guo,Hao;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/04
1/f3phase Noise (Pn) Corner  Common Mode (Cm)  Differential Mode (Dm)  Figure-of-merit (Fom)  Impulse Sensitivity Function (Isf)  Multi-lc-tank  One-dimensional (1d) Tuning  Single-turn Inductor  Voltage-controlled Oscillator (Vco)  
Affine Arithmetic-Based Coordinated Interval Power Flow of Integrated Transmission and Distribution Networks Journal article
IEEE TRANSACTIONS ON SMART GRID, 2020,Volume: 11,Issue: 5,Page: 4116-4132
Authors:  Kunjie Tang;  Shufeng Dong;  Chengzhi Zhu;  Yonghua Song
Favorite |  | TC[WOS]:7 TC[Scopus]:7 | Submit date:2021/05/10
Interval Power Flow  Integrated Transmission And Distribution Networks  Affine Arithmetic  Multistage  Uncertainty  
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 2,Page: 344-355
Authors:  Qi,Liang;  Jain,Ankesh;  Jiang,Dongyang;  Sin,Sai Weng;  Martins,Rui P.;  Ortmanns,Maurits
Favorite |  | TC[WOS]:9 TC[Scopus]:8 | Submit date:2021/03/09
Analog-to-digital converter (ADC)  continuous time (CT)  digital-to-analog converter (DAC) linearization  excess loop delay (ELD) compensation  filter  finite-impulse response (FIR)  multibit quantization  noise coupling (NC)  sturdy multistage noise-shaping (SMASH)  successive-approximation register (SAR)  
Portable NMR with Parallelism Journal article
Analytical Chemistry, 2020,Volume: 92,Issue: 2,Page: 2112-2120
Authors:  Lei,Ka Meng;  Ha,Dongwan;  Song,Yi Qiao;  Westervelt,Robert M.;  Martins,Rui;  Mak,Pui In;  Ham,Donhee
Favorite |  | TC[WOS]:5 TC[Scopus]:5 | Submit date:2021/03/09
Design of galvanic coupling intra-body communication transceiver using direct sequence spread spectrum technology Journal article
IEEE Access, 2020,Volume: 8,Page: 84123-84133
Authors:  Chen, W. K.;  Wei, Z. L.;  Gao, Y. M.;  Vasic, Z. Lucev;  Cifrek, M.;  Vai, M.I;  Du, M.;  Pun, S. H.
Favorite |  | TC[WOS]:5 TC[Scopus]:7 | Submit date:2021/03/11
Intra-body Communication  Galvanic Coupling  Ibc Transceiver  Bit Error Rate  Direct Sequence Spread Spectrum (Dsss)  
Multibit sturdy mash δσ modulator with error-shaped segmented dacs for wideband low-power applications Conference paper
Proceedings of International Conference on ASIC
Authors:  Qi,Liang;  Sin,Sai Weng;  Martins,Rui Paulo
Favorite |  | TC[WOS]:0 TC[Scopus]:2 | Submit date:2021/03/09
A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 5,Page: 1351-1362
Authors:  Yang, Shiheng;  Yin, Jun;  Yi, Haidong;  Yu, Wei Han;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:16 TC[Scopus]:19 | Submit date:2021/10/28
Bluetooth Low Energy (Ble)  Cmos  Energy Harvesting  Master-slave Sampling Filter (Mssf)  Micropower Manager (Μpm)  Phase-locked Loop (Pll)  Power Amplifier (Pa)  Power Gating  Transmitter (Tx)  Ultralow-voltage (Ulv)  Voltage-controlled Oscillator (Vco)  
A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 4,Page: 1161-1172
Authors:  Wang,Biao;  Sin,Sai Weng;  Seng-Pan,S. P.U.;  Maloberti,Franco;  Martins,Rui P.
Favorite |  | TC[WOS]:14 TC[Scopus]:16 | Submit date:2021/03/09
Analog-to-digital converter (ADC)  data weighting average  dynamic element matching (DEM)  high linearity  incremental ADC (IADC)  linear-exponential accumulation  mismatch error  multi-bit  notch  sigma delta  two phase