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A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3093-3097
Authors:  Huang, Yunbo;  Chen, Yong;  Jiao, Hailong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:2 | Submit date:2021/09/20
Cmos  Narrow Pulse Shielding  Reference (Ref) Feedthrough Suppression  Sampling Phase-locked Loop (S-pll)  T-shape Switch  Type-i  Voltage-controlled Oscillator (Vco)  
A 1.55-to-32-gb/s four-lane transmitter with 3-tap feed forward equalizer and shared pll in 28-nm cmos Journal article
Electronics (Switzerland), 2021,Volume: 10,Issue: 16
Authors:  Cai, Chen;  Zheng, Xuqiang;  Chen, Yong;  Wu, Danyu;  Luan, Jian;  Lu, Dechao;  Zhou, Lei;  Wu, Jin;  Liu, Xinyu
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/10/28
Cmos  Feed-forward Equalizer (Ffe)  High-speed Serial Interface  Phase-locked Loop (Pll)  Transmitter (Tx)  Voltage-controlled Oscillator (Vco)  
A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 6,Page: 2307-2316
Authors:  Yang, Zunsong;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2021/09/20
CMOS  current-reuse sampling phase detector (CRS-PD)  integrated jitter  loop filter (LF)  master-slave sampling filter (MSSF)  master-slave sampling phase detector (MSS-PD)  phase noise (PN)  Phase-locked loop (PLL)  reference spur  ring voltage-controlled oscillator (VCO)  type-I  type-II  
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:0 | Submit date:2021/03/09
Bang- Bang Clock And Data Recovery (Bbcdr)  Bang-bang Phase Detector (Bbpd)  Cmos  Four- And Eight-level Pulse Amplitude Modulation (Pam-4/-8)  Half Rate  Hogge And alexAnder Pd  Jitter Tolerance (Jtol).  Jitter Transfer Function (Jtf)  Non-return-to-zero (Nrz)  Strongarm Comparator  
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS Conference paper
Proceedings of the Custom Integrated Circuits Conference, Boston, MA, USA, 22-25 March 2020
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:2 | Submit date:2021/03/04
Acquisition Speed  Alexander Phase Detector (Pd)  Bang-bang  Bang-bang Clock And Data Recovery (Cdr)  Charge Pump (Cp)  Frequency Detector (Fd)  Full-rate  Jitter Tolerance (Jtf)  Jitter Transfer Function (Jtf)  Single Loop  Strobe Point (Sp)  
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique Conference paper
Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption, Bangkok, Thailand, 11-14 Nov. 2019
Authors:  Kong,Lingshan;  Chen,Yong;  Yu,Haohong;  Pan,Quan;  Boon,Chirn Chye;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/09
Bandwidth (Bw)  Cmos  High-speed Transceiver  Negative Capacitance  Peak-to-peak Jitter  Pseudo-current Steering  Variable-gain Amplifier (Vga)  Wide-tuning Gain Control  
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector Journal article
IEEE Access, 2019,Volume: 8,Page: 2222-2232
Authors:  Yang,Zunsong;  Chen,Yong;  Yang,Shiheng;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:6 TC[Scopus]:5 | Submit date:2021/03/09
Cmos  Divider-by-4  Dual Loop  Dynamic Latch  Figure-of-merit (Fom)  Frequency Detector (Fd)  Millimeter (Mm)-wave  Phase Detector (Pd)  Phase-locked Loop (Pll)  Voltage-controlled Oscillator (Vco)  Voltage-to-current Converter (Vic)  
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS Conference paper
Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption, Bangkok, Thailand, 11-14 Nov. 2019
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/09
4-/8-level Pulse Amplitude Modulation (Pam-4/8)  Bang-bang Phase Detector (Bbpd)  Clock And Data Recovery (Cdr)  Half Rate  Non-return To Zero (Nrz)  Strongarm Comparator  Voltage-to-current (V/i) Converter  Xor  
A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 5,Page: 1351-1362
Authors:  Yang, Shiheng;  Yin, Jun;  Yi, Haidong;  Yu, Wei Han;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:22 TC[Scopus]:19 | Submit date:2021/10/28
Bluetooth Low Energy (Ble)  Cmos  Energy Harvesting  Master-slave Sampling Filter (Mssf)  Micropower Manager (Μpm)  Phase-locked Loop (Pll)  Power Amplifier (Pa)  Power Gating  Transmitter (Tx)  Ultralow-voltage (Ulv)  Voltage-controlled Oscillator (Vco)  
16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur Conference paper
2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, USA, 17-21 Feb. 2019
Authors:  Zunsong Yang;  Yong Chen;  Shiheng Yang;  Pui-In Mak;  Rui P. Martins
Favorite |  | TC[WOS]:0 TC[Scopus]:30 | Submit date:2019/03/13