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A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3108-3112
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In;  Li, Qiang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
analog phase-locked loop (PLL)  Area  charge-sharing integrator  CMOS  digital PLL  hybrid PLL  integer-N  integrator  jitter  ring oscillator  ultra-low power  
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Authors:  Chen, Peng;  Meng, Xi;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
ADPLL  Bandwidth  Bluetooth LE (BLE)  Circuit stability  DCO  DTC  fractional-N PLL  Gain  inverse-class-F  Jitter  low power  Oscillators  Phase locked loops  phase noise (PN)  Quantization (signal)  TDC  the IoT.  
A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 3753-3763
Authors:  Yang,Xiaofeng;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui Paulo
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2021/03/04
Calibration-free  Discrete-time  Gain Tracking  Jitter  Open-loop  Phase Noise Cancellation (Pnc)  Phase-locked Loop (Pll)  Pvt  Reference Spur  Ring Voltage-controlled Oscillator (Rvco)  
A FPGA-based power electronics controller for hybrid active power filters Conference paper
Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Macau, 6-7 Oct. 2011
Authors:  Bo Sun;  U-Fat Chio;  Chi-Seng Lam;  Ning-Yi Dai;  Man-Chung Wong;  Chi-Kong Wong;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins
Favorite |  | TC[WOS]:0 TC[Scopus]:3 | Submit date:2018/12/23