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A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 2,Page: 344-355
Authors:  Qi,Liang;  Jain,Ankesh;  Jiang,Dongyang;  Sin,Sai Weng;  Martins,Rui P.;  Ortmanns,Maurits
Favorite |  | TC[WOS]:3 TC[Scopus]:4 | Submit date:2021/03/09
Analog-to-digital converter (ADC)  continuous time (CT)  digital-to-analog converter (DAC) linearization  excess loop delay (ELD) compensation  filter  finite-impulse response (FIR)  multibit quantization  noise coupling (NC)  sturdy multistage noise-shaping (SMASH)  successive-approximation register (SAR)  
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector Journal article
IEEE Access, 2020,Volume: 8,Page: 2222-2232
Authors:  Yang,Zunsong;  Chen,Yong;  Yang,Shiheng;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:4 | Submit date:2021/03/09
CMOS  divider-by-4  dual loop  dynamic latch  figure-of-merit (FoM)  frequency detector (FD)  millimeter (mm)-wave  phase detector (PD)  phase-locked loop (PLL)  voltage-controlled oscillator (VCO)  voltage-to-current converter (VIC)  
Dual Active-Feedback Frequency Compensation for Output-Capacitorless LDO with Transient and Stability Enhancement in 65-nm CMOS Journal article
IEEE Transactions on Power Electronics, 2020,Volume: 35,Issue: 1,Page: 415-429
Authors:  Li,Guangxiang;  Qian,Huimin;  Guo,Jianping;  Mo,Bing;  Lu,Yan;  Chen,Dihu
Favorite |  | TC[WOS]:9 TC[Scopus]:10 | Submit date:2021/03/11
Capacitorless  dual active-feedback frequency compensation (DAFFC)  low-dropout regulator (LDO)  stability  telescopic cascode output stage  
Dual circularly polarized loop antenna using a pair of resonant even-modes Journal article
International Journal of RF and Microwave Computer-Aided Engineering, 2019,Volume: 29,Issue: 6
Authors:  Xu,Lu;  Lu,Wen Jun;  Yuan,Cheng Ying;  Zhu,Lei
Favorite |  | TC[WOS]:6 TC[Scopus]:6 | Submit date:2021/03/09
dual circularly polarized antennas  even-mode resonant  square loop antenna  
Dual circularly polarized loop antenna using a pair of resonant even modes Journal article
International Journal of RF and Microwave Computer-Aided Engineering, 2019,Volume: 29,Issue: 6
Authors:  Lu Xu;  Wen‐Jun Lu;  Cheng‐Ying Yuan;  Lei Zhu
Favorite |  | TC[WOS]:6 TC[Scopus]:6 | Submit date:2019/07/23
Dual Circularly Polarized Antennas  Even-mode Resonant  Square Loop Antenna  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:  Yang S.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite |  | TC[WOS]:10 TC[Scopus]:10 | Submit date:2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 10,Page: 3196-3206
Authors:  Kong L.;  Chen Y.;  Boon C.C.;  Mak P.-I.;  Martins R.P.
Favorite |  | TC[WOS]:6 TC[Scopus]:9 | Submit date:2019/02/11
Automatic Gain Control (Agc) Amplifier  Bipolar Junction Transistors (Bjts)  Cmos  Db-linear  Dynamic Range  Negative Exponential Generator (Neg)  Pseudo-exponential Function  Rational Approximation  Taylor Series  
An 8.8-GS/s 8b time-interleaved SAR ADC with 50-dB SFDR using complementary dual-loop-assisted buffers in 28nm CMOS Conference paper
Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Authors:  Wang X.S.;  Chan C.-H.;  Du J.;  Wong C.-H.;  Li Y.;  Du Y.;  Kuan Y.-C.;  Hu B.;  Chang M.-C.F.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/14
A digital LDO with Co-SA logics and TSPC dynamic latches for fast transient response Journal article
IEEE Solid-State Circuits Letters, 2018,Volume: 1,Issue: 6,Page: 154-157
Authors:  Zhao,Lei;  Lu,Yan;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:8 | Submit date:2021/03/09
Continuous-time comparator  digital low-dropout regulator (DLDO)  dynamic logic  transient response  true single-phase clock (TSPC) latch  
A Dual-Loop Digital LDO Regulator with Asynchronous-Flash Binary Coarse Tuning Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems, Florence, ITALY, MAY 27-30, 2018
Authors:  Huang Y.;  Lu Y.;  Maloberti F.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:7 | Submit date:2019/02/11
Asynchronous Flash  Coarse Tuning  Digital Low-dropout Regulator  Ldo  Power Management