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Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Authors:  Chen, Peng;  Yin, Jun;  Zhang, Feifei;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
All-digital PLL (ADPLL)  build-in self-test (BIST)  Capacitance  Clocks  Delays  digital-to-time converter (DTC)  fractional spur  jitter  Loading  Logic gates  mismatch  Monte Carlo methods  noise shaping  Phase frequency detectors  phase/frequency detector (PFD)  self calibration  time-to-digital converter (TDC).  
Review of Analog-Assisted-Digital and Digital-Assisted-Analog Low Dropout Regulators Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 1,Page: 24-29
Authors:  Huang,Mo;  Lu,Yan;  Martins,Rui P.
Favorite |  | TC[WOS]:4 TC[Scopus]:2 | Submit date:2021/03/04
Analog-assisted-digital  Digital-assisted-analog  Low Dropout Regulator  Power Supply Rejection  Transient Response  
A Fast Response Digital Low-Dropout Regulator Based on Enhanced Analog Assisted Loop Conference paper
Proceedings of 2020 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2020, Nanjing, China, 23-25 Nov. 2020
Authors:  Chen, Ruipeng;  Zhou, Shaolin;  Wu, Zhaohui;  Li, Bin;  Huang, Mo
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/10/28
Current Buffer (Cb)  Digital Low Drop-out Regulator  Enhanced Analog Assisted (E-aa)  Power Management  Switch Compensated Register (Scr)  
An NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 4041-4052
Authors:  Ma,Xiaofei;  Lu,Yan;  Li,Qiang;  Ki,Wing Hung;  Martins,Rui P.
Favorite |  | TC[WOS]:5 TC[Scopus]:5 | Submit date:2021/03/04
Analog Assisted (Aa)  Coarse/fine Tuning  Digital Control  Digital Low-dropout Regulator (Ldo)  Fully Integrated Voltage Regulator (Fivr)  Limit Cycle Oscillation (Lco)  Nmos Ldo  Nonlinear Control  Output-capacitor-free  
A 2nd-Order Noise-Shaping SAR ADC with Lossless Dynamic Amplifier Assisted Integrator Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2020,Volume: 67,Issue: 10,Page: 1819-1823
Authors:  Zhang, Yanbo;  Liu, Shubin;  Tian, Binbin;  Zhu, Yan;  Chan, Chi Hang;  Zhu, Zhangming
Favorite |  | TC[WOS]:3 TC[Scopus]:3 | Submit date:2021/12/06
Analog-to-digital Converter (Adc)  Dynamic Amplifier  Lossless Integrator  Lossy Integrator  Noise Shaping (Ns)  Oversampling  Ping Pong  Successive Approximation Register (Sar)  
A SAR-ADC-Assisted DC-DC Buck Converter with Fast Transient Recovery Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2020,Volume: 67,Issue: 9,Page: 1669-1673
Authors:  Zeng,Wen Liang;  Bonizzoni,Edoardo;  Wu,Chi Wa;  Lam,Chi Seng;  Sin,Sai Weng;  Chio,U. Fat;  Maloberti,Franco;  Martins,Rui Paulo
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2021/03/04
Adc  Current Pump  Additional Loop Compensation  Buck Converter  Dcm  Bond-wire Inductor  Fast Transient Recovery  
A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC with Dynamic Gm-R-Based Amplifier Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 2,Page: 322-332
Authors:  Jiang,Wenning;  Zhu,Yan;  Zhang,Minglei;  Chan,Chi Hang;  Martins,Rui Paulo
Favorite |  | TC[WOS]:9 TC[Scopus]:9 | Submit date:2021/03/09
Analog-to-digital Converter (Adc)  Gm-r Amplifier  Pipelined-successive Approximation Register (Sar) Adc  Residue Amplifier (Ra)  Sar  Sar-assisted Pipelined Adc  Temperature Compensation  
A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 2,Page: 312-321
Authors:  Song,Yan;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite |  | TC[WOS]:9 TC[Scopus]:8 | Submit date:2021/03/09
Alternative Loading Capacitor (Alc)  Analog-to-digital Converter (Adc)  Multiplying Digital-to-analog Converter (Mdac) Reusing  Noise Shaping (Ns)  Successive Approximation Register (Sar)-assisted Pipeline  
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 2,Page: 344-355
Authors:  Qi,Liang;  Jain,Ankesh;  Jiang,Dongyang;  Sin,Sai Weng;  Martins,Rui P.;  Ortmanns,Maurits
Favorite |  | TC[WOS]:12 TC[Scopus]:8 | Submit date:2021/03/09
Analog-to-digital Converter (Adc)  Continuous Time (Ct)  Digital-to-analog Converter (Dac) Linearization  Excess Loop Delay (Eld) Compensation  Filter  Finite-impulse Response (Fir)  Multibit Quantization  Noise Coupling (Nc)  Sturdy Multistage Noise-shaping (Smash)  Successive-approximation Register (Sar)  
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC Journal article
IEEE Journal of Solid-State Circuits, 2020
Authors:  Song,Yan;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:1 | Submit date:2021/03/09
Analog-to-digital converter (ADC)  Calibration  Capacitors  Gain  noise-shaping (NS)  offset calibration  Pipelines  Registers  successive approximation register (SAR)-assisted pipeline  System-on-chip  time interleaving.  Transfer functions