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A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3108-3112
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In;  Li, Qiang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
analog phase-locked loop (PLL)  Area  charge-sharing integrator  CMOS  digital PLL  hybrid PLL  integer-N  integrator  jitter  ring oscillator  ultra-low power  
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Authors:  Chen, Peng;  Meng, Xi;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
ADPLL  Bandwidth  Bluetooth LE (BLE)  Circuit stability  DCO  DTC  fractional-N PLL  Gain  inverse-class-F  Jitter  low power  Oscillators  Phase locked loops  phase noise (PN)  Quantization (signal)  TDC  the IoT.  
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Authors:  Chen, Peng;  Yin, Jun;  Zhang, Feifei;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
All-digital PLL (ADPLL)  build-in self-test (BIST)  Capacitance  Clocks  Delays  digital-to-time converter (DTC)  fractional spur  jitter  Loading  Logic gates  mismatch  Monte Carlo methods  noise shaping  Phase frequency detectors  phase/frequency detector (PFD)  self calibration  time-to-digital converter (TDC).  
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 9,Page: 3307-3316
Authors:  Un,Ka Fai;  Qi,Gengzhen;  Yin,Jun;  Yang,Shiheng;  Yu,Shupeng;  Ieong,Chio In;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:3 | Submit date:2021/03/09
Bang-bang  Digital Phase-locked Loop (Dpll)  Digital-to-time Converter (Dtc)  Gain Calibration  Ring Vco  Ultra-fast Settling  Ultra-low-power (Ulp)  Voltage-controlled Oscillator (Vco)  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:  Yang S.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite |  | TC[WOS]:12 TC[Scopus]:14 | Submit date:2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 0.0056mm2all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrmsJitter and -249dB FOM Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, United states, 2 11, 2018 - 2 15, 2018
Authors:  Yang, Shiheng;  Yin, Jun;  Mak, Pui-In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:15 | Submit date:2018/11/06
A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, FEB 11-15, 2018
Authors:  Shiheng Yang;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite |  | TC[WOS]:14 TC[Scopus]:15 | Submit date:2019/02/11
A CMOS Delta-Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015,Volume: 62,Issue: 7,Page: 1716-1725
Authors:  Huang,Mo;  Chen,Dihu;  Guo,Jianping;  Ye,Hui;  Xu,Ken;  Liang,Xiaofeng;  Lu,Yan
Favorite |  | TC[WOS]:9 TC[Scopus]:10 | Submit date:2021/03/11
Delta-sigma phase locked loop (PLL)  modulation bandwidth calibration  transmitters  
A CMOS Delta-Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015,Volume: 62,Issue: 7,Page: 1716-1725
Authors:  Huang M.;  Chen D.;  Guo J.;  Ye H.;  Xu K.;  Liang X.;  Lu Y.
Favorite |  | TC[WOS]:9 TC[Scopus]:10 | Submit date:2019/02/14
Delta-sigma Phase Locked Loop (Pll)  Modulation Bandwidth Calibration  Transmitters  
Design of digital phase locked sensor loop for paralleled inverters Journal article
Sensor Letters, 2013,Volume: 11,Issue: 11,Page: 2131-2133
Authors:  Huang, Baoshan;  Xu, Wei;  Zou, Xinfeng;  Yuan, Shihua
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2018/11/06