UM

Browse/Search Results:  1-4 of 4 Help

Selected(0)Clear Items/Page:    Sort:
Near-Optimal Decoding of Incremental Delta-Sigma ADC Output Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 3670-3680
Authors:  Wang,Bo;  Law,Man Kay;  Belhaouari,Samir Brahim;  Bermak,Amine
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2021/03/11
decimation filter  delta-sigma modulator  IDC  incremental ADC  noise penalty factor  optimal filter  Reconstruction filter  thermal noise averaging  
A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 4,Page: 1307-1319
Authors:  Ieong, Chio-In;  Li, Mingzhong;  Law, Man-Kay;  Mak, Pui-In;  Vai, Mang I.;  Martins, Rui P.
Favorite |  | TC[WOS]:16 TC[Scopus]:17 | Submit date:2018/10/30
Adaptive Temporal Decimation (Atd)  Data Compression Processor  Electrocardiogram (Ecg)  Near-threshold Digital Logics  Wavelet Shrinkage (Ws)  Wavelet Transform (Wt)  
A 2.2μW 15b incremental delta-sigma ADC with output-driven input segmentation Conference paper
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Macao, PEOPLES R CHINA, JAN 25-28, 2016
Authors:  Wang B.;  Law M.K.;  Mohamad S.;  Bermak A.
Favorite |  | TC[WOS]:1 TC[Scopus]:2 | Submit date:2019/02/14
Dual-feedback Σs Modulator  Incremental Delta-sigma Adc  Integrator Multiplexing  Low Power Adc  
Interactive IIR SC multirate compiler applied to multistage decimator design Journal article
Journal of Circuits, Systems and Computers, 2007,Volume: 16,Issue: 4,Page: 517-525
Authors:  PHILLIP N. CHEONG;  R. P. MARTINS
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2019/02/11
Iir Filter  Multistage  Switched Capacitors  Decimator Design  Compiler