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A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3108-3112
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In;  Li, Qiang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
analog phase-locked loop (PLL)  Area  charge-sharing integrator  CMOS  digital PLL  hybrid PLL  integer-N  integrator  jitter  ring oscillator  ultra-low power  
A 0.35-V 5,200-μm² 2.1-MHz Temperature- Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator Journal article
IEEE Journal of Solid-State Circuits, 2021
Authors:  Lei, Ka Meng;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Asymmetric RC network  Circuit stability  CMOS  energy-harvesting  Internet-of-Things (IoT)  Logic gates  MOS devices  Oscillators  relaxation oscillator (RxO)  Resilience  Stability criteria  swing-boosting  temperature resilience  Thermal stability  ultra-low-power  ultra-low-voltage (ULV).  
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Authors:  Chen, Peng;  Meng, Xi;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
ADPLL  Bandwidth  Bluetooth LE (BLE)  Circuit stability  DCO  DTC  fractional-N PLL  Gain  inverse-class-F  Jitter  low power  Oscillators  Phase locked loops  phase noise (PN)  Quantization (signal)  TDC  the IoT.  
An NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 4041-4052
Authors:  Ma,Xiaofei;  Lu,Yan;  Li,Qiang;  Ki,Wing Hung;  Martins,Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:4 | Submit date:2021/03/04
Analog assisted (AA)  coarse/fine tuning  digital control  digital low-dropout regulator (LDO)  fully integrated voltage regulator (FIVR)  limit cycle oscillation (LCO)  NMOS LDO  nonlinear control  output-capacitor-free  
A 470-nA Quiescent Current and 92.7%/94.7% Efficiency DCT/PWM Control Buck Converter with Seamless Mode Selection for IoT Application Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 4085-4098
Authors:  Zeng,Wen Liang;  Ren,Yuan;  Lam,Chi Seng;  Sin,Sai Weng;  Che,Weng Keong;  Ding,Ran;  Martins,Rui Paulo
Favorite |  | TC[WOS]:4 TC[Scopus]:3 | Submit date:2021/03/04
buck converter  discontinuous conduction mode (DCM)  double clock time (DCT) control  Internet of things (IoT)  mode selection  pulse-width-modulation (PWM) current mode control  ultra-low-quiescent current  
A Fully Integrated LDO with 50-mV Dropout for Power Efficiency Optimization Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2020,Volume: 67,Issue: 4,Page: 725-729
Authors:  Ma,Xiaofei;  Lu,Yan;  Li,Qiang
Favorite |  | TC[WOS]:6 TC[Scopus]:6 | Submit date:2021/03/11
high power efficiency  Low-dropout regulator  output-capacitor-free  ultra-fast response  
1-kV Sputtered p-NiO/n-Ga2O3 Heterojunction Diodes with an Ultra-Low Leakage Current below μ A/cm2 Journal article
IEEE Electron Device Letters, 2020,Volume: 41,Issue: 3,Page: 449-452
Authors:  Lu, Xing;  Zhou, Xianda;  Jiang, Huaxing;  Ng, Kar Wei;  Chen, Zimin;  Pei, Yanli;  Lau, Kei May;  Wang, Gang
Favorite |  | TC[WOS]:26 TC[Scopus]:29 | Submit date:2021/09/17
breakdown voltage  heterojunction  NiO  p-n diode  reverse leakage current  β-Ga2O3  
A 1-nW Ultra-Low Voltage Subthreshold CMOS Voltage Reference with 0.0154%/V Line Sensitivity Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 10,Page: 1653-1657
Authors:  Lin,Jie;  Wang,Lidan;  Zhan,Chenchang;  Lu,Yan
Favorite |  | TC[WOS]:12 TC[Scopus]:12 | Submit date:2021/03/11
CMOS voltage reference  line sensitivity  low power  low voltage  subthreshold  
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 9,Page: 3307-3316
Authors:  Un,Ka Fai;  Qi,Gengzhen;  Yin,Jun;  Yang,Shiheng;  Yu,Shupeng;  Ieong,Chio In;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:3 | Submit date:2021/03/09
bang-bang  Digital phase-locked loop (DPLL)  digital-to-time converter (DTC)  gain calibration  ring VCO  ultra-fast settling  ultra-low-power (ULP)  voltage-controlled oscillator (VCO)  
A 0.5-V-supply, 37.8-nW, 17.6-ppm/°C switched-capacitor bandgap reference with second-order curvature compensation Journal article
Microelectronics Journal, 2019,Volume: 87,Page: 136-143
Authors:  Liu,Yang;  Li,Bin;  Chen,Zhaoquan;  Chen,Zhijian;  Huang,Mo;  Lu,Yan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/11
Bandgap reference  High order curvature compensation  Switched-capacitor  Ultra-low power