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A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 6,Page: 1588-1598
Authors:  Wang,Wei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite |  | TC[WOS]:1 TC[Scopus]:2 | Submit date:2020/12/04
Analog-to-digital conversion (ADC)  continuous-time delta-sigma modulator (CT-DSM)  preliminary sampling and quantization (PSQ) technique  single amplifier biquad (SAB)  successiveapproximation-register (SAR) architecture-based quantizer (QTZ)  
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 5,Page: 1223-1234
Authors:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  Rui Paulo Martins
Favorite |  | TC[WOS]:22 TC[Scopus]:24 | Submit date:2019/02/11
Offset Calibration  Pipelined-successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Sar Logic  
A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration Conference paper
2011 Proceedings of the ESSCIRC (ESSCIRC), Helsinki, Finland, 12-16 Sept. 2011
Authors:  Chio U.-F.;  Chan C.-H.;  Choi H.-L.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2019/02/11
Design and experimental verification of a power effective Flash-SAR subranging ADC Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2010,Volume: 57,Issue: 8,Page: 607-611
Authors:  U-Fat Chio;  He-Gong Wei;  Yan Zhu;  Sai-Weng Sin;  Seng-Pan U;  R. P. Martins;  Franco Maloberti
Favorite |  | TC[WOS]:23 TC[Scopus]:30 | Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Digital Error Correction (Dec)  Flash Adc  Sar Adc  Subranging Adc