UM

Browse/Search Results:  1-10 of 11 Help

Selected(0)Clear Items/Page:    Sort:
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC with <1.5-ps Uncalibrated Quantization Steps Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 12,Page: 3225-3235
Authors:  Zhang,Minglei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/04
Analog-to-digital converter (ADC)  and temperature (PVT) robustness  high-speed ADC  metastability  process  supply voltage  time interpolation  time residue  time-domain ADC  time-to-digital converter (TDC)  
A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 3753-3763
Authors:  Yang,Xiaofeng;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui Paulo
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/04
calibration-free  discrete-time  gain tracking  Jitter  open-loop  phase noise cancellation (PNC)  phase-locked loop (PLL)  PVT  reference spur  ring voltage-controlled oscillator (RVCO)  
3.5 A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Zhang,Minglei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:10 | Submit date:2021/03/09
16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur Conference paper
2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, USA, 17-21 Feb. 2019
Authors:  Zunsong Yang;  Yong Chen;  Shiheng Yang;  Pui-In Mak;  Rui P. Martins
Favorite |  | TC[WOS]:0 TC[Scopus]:20 | Submit date:2019/03/13
A Regulation-Free Sub-0.5-V 16-/24-MHz Crystal Oscillator with 14.2-nJ Startup Energy and 31.8-μW Steady-State Power Journal article
IEEE Journal of Solid-State Circuits, 2018,Volume: 53,Issue: 9,Page: 2624-2635
Authors:  Lei K.-M.;  Mak P.-I.;  Law M.-K.;  Martins R.P.
Favorite |  | TC[WOS]:10 TC[Scopus]:11 | Submit date:2019/02/11
Bluetooth Low-energy (Ble)  Chirping  Cmos  Crystal Oscillator (Xo)  Duty-cycling  Energy Harvesting (Eh)  Fast Startup  Internet-of-things (Iot)  Ultralow Power (Ulp)  Ultralow Voltage (Ulv)  
A 0.0056mm2all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrmsJitter and -249dB FOM Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, United states, 2 11, 2018 - 2 15, 2018
Authors:  Yang, Shiheng;  Yin, Jun;  Mak, Pui-In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:13 | Submit date:2018/11/06
A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, FEB 11-15, 2018
Authors:  Shiheng Yang;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite |  | TC[WOS]:14 TC[Scopus]:13 | Submit date:2019/02/11
A Calibration Scheme for Stability of Self-biased Ring Amplifier Conference paper
Authors:  Yan, Rongshen;  Chan, Chi-Hang;  Sin, Sai-Weng;  Seng-Pan, U.;  Martins, R. P.;  Wang, ZH;  Xie, WH
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2018/10/30
Calibration  Self-biased Ring Amplifier  PVT Variations  Oscillation Detection  Programmable Resistor  
Adaptive On/Off Delay-Compensated Active Rectifiers for Wireless Power Transfer Systems Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 3,Page: 712-723
Authors:  Cheng L.;  Ki W.-H.;  Lu Y.;  Yim T.-S.
Favorite |  | TC[WOS]:60 TC[Scopus]:70 | Submit date:2019/02/14
Active Rectifier  Comparator Delay  Delay Compensation  Inductive Coupling  Pvt Variations  Resonant Wireless Power Transfer (R-wpt)  Reverse Current Control  
Energy Optimized Subthreshold VLSI Logic Family with Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015,Volume: 23,Issue: 12,Page: 3119-3123
Authors:  Li M.-Z.;  Ieong C.-I.;  Law M.-K.;  Mak P.-I.;  Vai M.-I.;  Pun S.-H.;  Martins R.P.
Favorite |  | TC[WOS]:13 TC[Scopus]:17 | Submit date:2019/02/11
Cmos  Device Sizing  Electrocardiography (Ecg)  Finite Impulse Response (Fir) Filter  Inverse Narrow Width (Inw)  Logical Effort  Process-voltage-temperature (Pvt) Variations  Subthreshold Standard Logic Library  Ultralow Energy  Ultralow Voltage.