UM

Browse/Search Results:  1-10 of 42 Help

Selected(0)Clear Items/Page:    Sort:
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Authors:  Chen, Peng;  Yin, Jun;  Zhang, Feifei;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
All-digital PLL (ADPLL)  build-in self-test (BIST)  Capacitance  Clocks  Delays  digital-to-time converter (DTC)  fractional spur  jitter  Loading  Logic gates  mismatch  Monte Carlo methods  noise shaping  Phase frequency detectors  phase/frequency detector (PFD)  self calibration  time-to-digital converter (TDC).  
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC Journal article
IEEE Journal of Solid-State Circuits, 2020
Authors:  Song,Yan;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
Analog-to-digital converter (ADC)  Calibration  Capacitors  Gain  noise-shaping (NS)  offset calibration  Pipelines  Registers  successive approximation register (SAR)-assisted pipeline  System-on-chip  time interleaving.  Transfer functions  
A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS Conference paper
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Authors:  Wang,Biao;  Sin,Sai Weng;  Seng-Pan,U.;  Maloberti,Franco;  Martins,R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
Data Weighted Averaging  Linear-exponential  Multi-Bit Incremental ADC  Positive Feedback  
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 9,Page: 3307-3316
Authors:  Un,Ka Fai;  Qi,Gengzhen;  Yin,Jun;  Yang,Shiheng;  Yu,Shupeng;  Ieong,Chio In;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:3 | Submit date:2021/03/09
bang-bang  Digital phase-locked loop (DPLL)  digital-to-time converter (DTC)  gain calibration  ring VCO  ultra-fast settling  ultra-low-power (ULP)  voltage-controlled oscillator (VCO)  
A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 4,Page: 1161-1172
Authors:  Wang,Biao;  Sin,Sai Weng;  Seng-Pan,S. P.U.;  Maloberti,Franco;  Martins,Rui P.
Favorite |  | TC[WOS]:14 TC[Scopus]:16 | Submit date:2021/03/09
Analog-to-digital converter (ADC)  data weighting average  dynamic element matching (DEM)  high linearity  incremental ADC (IADC)  linear-exponential accumulation  mismatch error  multi-bit  notch  sigma delta  two phase  
Unconventional solution-phase epitaxial growth of organic-inorganic hybrid perovskite nanocrystals on metal sulfide nanosheets Journal article
Science China Materials, 2019,Volume: 62,Issue: 1,Page: 43-53
Authors:  Zhipeng Zhang;  Fangfang Sun;  Zhaohua Zhu;  Jie Dai;  Kai Gao;  Qi Wei;  Xiaotong Shi;  Qian Sun;  Yan Yan;  Hai Li;  Haidong Yu;  Guichuan Xing;  Xiao Huang;  Wei Huang
Favorite |  | TC[WOS]:13 TC[Scopus]:11 | Submit date:2019/04/08
Epitaxial Growth  Organic-inorganic Hybrid Perovskite  Paper-based Photodetector  Transition Metal Chalcogenide  
Unconventional solution-phase epitaxial growth of organic-inorganic hybrid perovskite nanocrystals on metal sulfide nanosheets 非传统溶液外延法在金属硫化物纳米片表面生长有机无机杂化钙钛矿纳米晶 Journal article
Science China Materials, 2019,Volume: 62,Issue: 1,Page: 43-53
Authors:  Zhang, Zhipeng;  Sun, Fangfang;  Zhu, Zhaohua;  Dai, Jie;  Gao, Kai;  Wei, Qi;  Shi, Xiaotong;  Sun, Qian;  Yan, Yan;  Li, Hai;  Yu, Haidong;  Xing, Guichuan;  Huang, Xiao;  Huang, Wei
Favorite |  | TC[WOS]:13 TC[Scopus]:11 | Submit date:2021/09/10
epitaxial growth  organic-inorganic hybrid perovskite  paper-based photodetector  transition metal chalcogenide  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:  Yang S.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite |  | TC[WOS]:12 TC[Scopus]:13 | Submit date:2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Wang B.;  Sin S.-W.;  Seng-Pan U.;  Malobertr F.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:6 | Submit date:2019/02/11
Fabrication and characteristics of graphene-reinforced silver nanowire/polybenzoxazine/epoxy copolymer composite thin films Journal article
POLYMER INTERNATIONAL, 2018,Volume: 67,Issue: 8,Page: 1081-1093
Authors:  Chou, Tsung-Yu;  Tsai, Hung-Yin;  Hsu, Chen-Hao;  Yip, Ming-Chuen
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2018/10/30
silver nanowires  graphene  polybenzoxazine  epoxy  electrical conductivity  thermal oxidation