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Voltage Source Rectifiers with Power Synchronization Control Conference paper
2020 4th International Conference on HVDC, HVDC 2020
Authors:  Chen,Zhe;  Zhu,Miao;  Hou,Chuanchuan;  Dai,Ningyi;  Cai,Xu
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
direct current control  phase locked loop  power synchronization control  voltage source PWM rectifier  weak grid  
A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 3753-3763
Authors:  Yang,Xiaofeng;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui Paulo
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/04
calibration-free  discrete-time  gain tracking  Jitter  open-loop  phase noise cancellation (PNC)  phase-locked loop (PLL)  PVT  reference spur  ring voltage-controlled oscillator (RVCO)  
A 9mW 54.9-to-63.5GHz Current-Reuse LO Generator with a 186.7dBc/Hz FoM by Unifying a 20GHz 3rd-Harmonic-Rich Current-Output VCO, a Harmonic-Current Filter and a 60GHz TIA Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Fan,Chao;  Yin,Jun;  Lim,Chee Cheow;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:4 | Submit date:2021/03/04
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector Journal article
IEEE Access, 2020,Volume: 8,Page: 2222-2232
Authors:  Yang,Zunsong;  Chen,Yong;  Yang,Shiheng;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:4 | Submit date:2021/03/09
CMOS  divider-by-4  dual loop  dynamic latch  figure-of-merit (FoM)  frequency detector (FD)  millimeter (mm)-wave  phase detector (PD)  phase-locked loop (PLL)  voltage-controlled oscillator (VCO)  voltage-to-current converter (VIC)  
A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM Journal article
IEEE Solid-State Circuits Letters, 2020,Volume: 3,Page: 494-497
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
CMOS  in-band phase noise (PN)  narrow-pulse-sampling (NPS)  phase-locked loop (PLL)  reference (REF) spur  T-shape switch  type-I  voltage-controlled oscillator (VCO)  
A 0.003-mm2 440fsRMS-Jitter and-64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Conference paper
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:5 | Submit date:2021/03/09
phase detector  phase locked loop (PLL)  reference spur  Ring voltage-controlled oscillator (VCO)  RMS jitter  
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 9,Page: 3307-3316
Authors:  Un,Ka Fai;  Qi,Gengzhen;  Yin,Jun;  Yang,Shiheng;  Yu,Shupeng;  Ieong,Chio In;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:3 | Submit date:2021/03/09
bang-bang  Digital phase-locked loop (DPLL)  digital-to-time converter (DTC)  gain calibration  ring VCO  ultra-fast settling  ultra-low-power (ULP)  voltage-controlled oscillator (VCO)  
16.3 A -246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation over PVT Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Yang,Xiaofeng;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:6 | Submit date:2021/03/09
16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur Conference paper
2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, USA, 17-21 Feb. 2019
Authors:  Zunsong Yang;  Yong Chen;  Shiheng Yang;  Pui-In Mak;  Rui P. Martins
Favorite |  | TC[WOS]:0 TC[Scopus]:20 | Submit date:2019/03/13
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2019,Page: 1 - 12
Authors:  Shiheng Yang;  Jun Yin;  Haidong Yi;  Wei-Han Yu;  Pui-In Mak;  Rui P. Martins
Favorite |  | TC[WOS]:14 TC[Scopus]:17 | Submit date:2019/03/12
Bluetooth Low Energy (Ble)  Cmos  Energy Harvesting  Master-slave Sampling Filter (Mssf)  Micropower Manager (Μpm)  Phase-locked Loop (Pll)  Power Amplifier (Pa)  Power Gating  Transmitter (Tx)  Ultralow-voltage (Ulv)  Voltage-controlled Oscillator (Vco)