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A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 2,Page: 157-161
Authors:  Jiang T.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite |  | TC[WOS]:5 TC[Scopus]:4 | Submit date:2019/02/14
Bootstrap (Bt)  Low Voltage  Non-overlapping Clock  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  
A 90nm CMOS Bio-Potential Signal Readout Front-End with Improved Powerline Interference Rejection Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems, Taipei, TAIWAN, MAY 24-27, 2009
Authors:  Chon-Teng Ma;  Pui-In Mak;  Mang-I Vai;  Peng-Un Mak;  Sio-Hang Pun;  Wan Feng;  R. P. Martins
Favorite |  | TC[WOS]:19 TC[Scopus]:24 | Submit date:2019/02/11
A 90nm CMOS bio-potential signal readout front-end with improved powerline interference rejection Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems
Authors:  Ma,Chon Teng;  Mak,Pui In;  Vai,Mang I.;  Mak,Peng Un;  Pun,Sio Hang;  Feng,Wan;  Martins,R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:24 | Submit date:2021/03/09