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A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3108-3112
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In;  Li, Qiang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
analog phase-locked loop (PLL)  Area  charge-sharing integrator  CMOS  digital PLL  hybrid PLL  integer-N  integrator  jitter  ring oscillator  ultra-low power  
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2021
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/10/28
Acquisition Speed  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Clocks  Cmos  Detectors  Four-level Pulse Amplitude Modulation (Pam-4)  Frequency Detector (Fd)  Frequency Modulation  Hybrid Control Circuit (Hcc)  Jitter  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Logic Gates  Phase Detector (Pd)  Strobe Point (Sp).  Switches  Voltage-controlled Oscillators  
A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3093-3097
Authors:  Huang, Yunbo;  Chen, Yong;  Jiao, Hailong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:2 | Submit date:2021/09/20
Cmos  Narrow Pulse Shielding  Reference (Ref) Feedthrough Suppression  Sampling Phase-locked Loop (S-pll)  T-shape Switch  Type-i  Voltage-controlled Oscillator (Vco)  
A 1.55-to-32-gb/s four-lane transmitter with 3-tap feed forward equalizer and shared pll in 28-nm cmos Journal article
Electronics (Switzerland), 2021,Volume: 10,Issue: 16
Authors:  Cai, Chen;  Zheng, Xuqiang;  Chen, Yong;  Wu, Danyu;  Luan, Jian;  Lu, Dechao;  Zhou, Lei;  Wu, Jin;  Liu, Xinyu
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/10/28
Cmos  Feed-forward Equalizer (Ffe)  High-speed Serial Interface  Phase-locked Loop (Pll)  Transmitter (Tx)  Voltage-controlled Oscillator (Vco)  
A 0.01-mm21.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase Conference paper
IEEE MTT-S International Microwave Symposium Digest
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Zheng, Xuqiang;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/12/08
bang-bang clock and data recovery (BBCDR)  clock selection  CMOS  frequency acquisition  frequency detector (FD)  reference (REF)  ring oscillator (RO)  strobe point (SP)  
A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 6,Page: 2307-2316
Authors:  Yang, Zunsong;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2021/09/20
CMOS  current-reuse sampling phase detector (CRS-PD)  integrated jitter  loop filter (LF)  master-slave sampling filter (MSSF)  master-slave sampling phase detector (MSS-PD)  phase noise (PN)  Phase-locked loop (PLL)  reference spur  ring voltage-controlled oscillator (VCO)  type-I  type-II  
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:0 | Submit date:2021/03/09
Bang- Bang Clock And Data Recovery (Bbcdr)  Bang-bang Phase Detector (Bbpd)  Cmos  Four- And Eight-level Pulse Amplitude Modulation (Pam-4/-8)  Half Rate  Hogge And alexAnder Pd  Jitter Tolerance (Jtol).  Jitter Transfer Function (Jtf)  Non-return-to-zero (Nrz)  Strongarm Comparator  
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Authors:  Chen, Peng;  Yin, Jun;  Zhang, Feifei;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
All-digital PLL (ADPLL)  build-in self-test (BIST)  Capacitance  Clocks  Delays  digital-to-time converter (DTC)  fractional spur  jitter  Loading  Logic gates  mismatch  Monte Carlo methods  noise shaping  Phase frequency detectors  phase/frequency detector (PFD)  self calibration  time-to-digital converter (TDC).  
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Authors:  Chen, Peng;  Meng, Xi;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
ADPLL  Bandwidth  Bluetooth LE (BLE)  Circuit stability  DCO  DTC  fractional-N PLL  Gain  inverse-class-F  Jitter  low power  Oscillators  Phase locked loops  phase noise (PN)  Quantization (signal)  TDC  the IoT.  
Correlation between Pathological Voice Onset and Voice Quality Based on Vocal Attack Time(VAT) and Multidimensional Voice Parameters Conference paper
PervasiveHealth: Pervasive Computing Technologies for Healthcare, Beijing China, September 11 - 13, 2020
Authors:  Wu, Nankai;  Cao, Qingsong;  Li, Huanzhe;  Hou, Xingquan;  Lo, Infat;  Kong, Jiangping
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/12/06
Electroglottography  Pathological Voice  Vocal Attack Time  Voice Onset  Voice Quality