UM

Browse/Search Results:  1-10 of 58 Help

Selected(0)Clear Items/Page:    Sort:
A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 3753-3763
Authors:  Yang,Xiaofeng;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui Paulo
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/04
calibration-free  discrete-time  gain tracking  Jitter  open-loop  phase noise cancellation (PNC)  phase-locked loop (PLL)  PVT  reference spur  ring voltage-controlled oscillator (RVCO)  
A 108 F2/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 3866-3879
Authors:  Zhao,Qiang;  Zheng,Wenhan;  Zhao,Xiaojin;  Cao,Yuan;  Zhang,Feng;  Law,Man Kay
Favorite |  | TC[WOS]:1 TC[Scopus]:2 | Submit date:2021/03/11
dynamic entropy source  full reconfigurability  high reliability  Physical unclonable function  resistive random access memory  true random number generator  
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS Conference paper
Proceedings of the Custom Integrated Circuits Conference
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/04
acquisition speed  Alexander phase detector (PD)  bang-bang  bang-bang clock and data recovery (CDR)  charge pump (CP)  frequency detector (FD)  full-rate  jitter tolerance (JTF)  jitter transfer function (JTF)  Single loop  strobe point (SP)  
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
bang- bang clock and data recovery (BBCDR)  bang-bang phase detector (BBPD)  CMOS  four- and eight-level pulse amplitude modulation (PAM-4/-8)  half rate  Hogge and Alexander PD  jitter tolerance (JTOL).  jitter transfer function (JTF)  non-return-to-zero (NRZ)  StrongARM comparator  
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector Journal article
IEEE Access, 2020,Volume: 8,Page: 2222-2232
Authors:  Yang,Zunsong;  Chen,Yong;  Yang,Shiheng;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2021/03/09
CMOS  divider-by-4  dual loop  dynamic latch  figure-of-merit (FoM)  frequency detector (FD)  millimeter (mm)-wave  phase detector (PD)  phase-locked loop (PLL)  voltage-controlled oscillator (VCO)  voltage-to-current converter (VIC)  
A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM Journal article
IEEE Solid-State Circuits Letters, 2020,Volume: 3,Page: 494-497
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
CMOS  in-band phase noise (PN)  narrow-pulse-sampling (NPS)  phase-locked loop (PLL)  reference (REF) spur  T-shape switch  type-I  voltage-controlled oscillator (VCO)  
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique Conference paper
Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption
Authors:  Kong,Lingshan;  Chen,Yong;  Yu,Haohong;  Pan,Quan;  Boon,Chirn Chye;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/09
bandwidth (BW)  CMOS  high-speed transceiver  negative capacitance  peak-to-peak jitter  pseudo-current steering  variable-gain amplifier (VGA)  wide-tuning gain control  
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS Conference paper
Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
4-/8-level pulse amplitude modulation (PAM-4/8)  bang-bang phase detector (BBPD)  clock and data recovery (CDR)  half rate  non-return to zero (NRZ)  StrongARM comparator  voltage-to-current (V/I) converter  XOR  
A 0.003-mm2 440fsRMS-Jitter and-64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Conference paper
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:4 | Submit date:2021/03/09
phase detector  phase locked loop (PLL)  reference spur  Ring voltage-controlled oscillator (VCO)  RMS jitter  
Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 10,Page: 2223-2236
Authors:  Ge,Xinyi;  Chen,Yong;  Zhao,Xiaoteng;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:6 TC[Scopus]:5 | Submit date:2021/03/09
Bang-bang clock and data recovery (BBCDR)  bang-bang phase detector (BBPD)  binary  Fourier series  jitter generation (JGEN)  jitter tolerance (JTOL)  jitter transfer function (JTF)  linear phase detector  loop filter (LF)  sinking area