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A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3108-3112
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In;  Li, Qiang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
analog phase-locked loop (PLL)  Area  charge-sharing integrator  CMOS  digital PLL  hybrid PLL  integer-N  integrator  jitter  ring oscillator  ultra-low power  
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2021
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/10/28
Acquisition Speed  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Clocks  Cmos  Detectors  Four-level Pulse Amplitude Modulation (Pam-4)  Frequency Detector (Fd)  Frequency Modulation  Hybrid Control Circuit (Hcc)  Jitter  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Logic Gates  Phase Detector (Pd)  Strobe Point (Sp).  Switches  Voltage-controlled Oscillators  
A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3093-3097
Authors:  Huang, Yunbo;  Chen, Yong;  Jiao, Hailong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:2 | Submit date:2021/09/20
Cmos  Narrow Pulse Shielding  Reference (Ref) Feedthrough Suppression  Sampling Phase-locked Loop (S-pll)  T-shape Switch  Type-i  Voltage-controlled Oscillator (Vco)  
A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS Conference paper
Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, Atlanta, GA, USA, 7-9 June 2021
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Wang, Lin;  Mak, Pui In;  Maloberti, Franco;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
4-level Pulse Amplitude Modulation (Pam-4)  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Cmos  Frequency Detector (Fd)  Half-rate  Negative (Nnc) Net Current  Positive (Pnc)  Reference Less  Single Loop  Zero (Znc)  
A 0.01-mm21.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase Conference paper
IEEE MTT-S International Microwave Symposium Digest
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Zheng, Xuqiang;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/12/08
bang-bang clock and data recovery (BBCDR)  clock selection  CMOS  frequency acquisition  frequency detector (FD)  reference (REF)  ring oscillator (RO)  strobe point (SP)  
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Authors:  Chen, Peng;  Yin, Jun;  Zhang, Feifei;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
All-digital PLL (ADPLL)  build-in self-test (BIST)  Capacitance  Clocks  Delays  digital-to-time converter (DTC)  fractional spur  jitter  Loading  Logic gates  mismatch  Monte Carlo methods  noise shaping  Phase frequency detectors  phase/frequency detector (PFD)  self calibration  time-to-digital converter (TDC).  
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS Conference paper
Proceedings of the Custom Integrated Circuits Conference, Boston, MA, USA, 22-25 March 2020
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:2 | Submit date:2021/03/04
Acquisition Speed  Alexander Phase Detector (Pd)  Bang-bang  Bang-bang Clock And Data Recovery (Cdr)  Charge Pump (Cp)  Frequency Detector (Fd)  Full-rate  Jitter Tolerance (Jtf)  Jitter Transfer Function (Jtf)  Single Loop  Strobe Point (Sp)  
An Intermittent Frequency Synthesizer with Accurate Frequency Detection for Fast Duty-Cycled Receivers Journal article
IEEE Access, 2020,Volume: 8,Page: 45148-45155
Authors:  Yin,Yadong;  El-Sankary,Kamal;  Chen,Zhizhang;  Gao,Yueming;  Vai,Mang I.;  Pun,Sio Hang
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/11
Duty Cycle  Frequency Detector  Frequency Synthesizer  Initial Phase Error  Phase-locked Loop  
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector Journal article
IEEE Access, 2019,Volume: 8,Page: 2222-2232
Authors:  Yang,Zunsong;  Chen,Yong;  Yang,Shiheng;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:6 TC[Scopus]:5 | Submit date:2021/03/09
Cmos  Divider-by-4  Dual Loop  Dynamic Latch  Figure-of-merit (Fom)  Frequency Detector (Fd)  Millimeter (Mm)-wave  Phase Detector (Pd)  Phase-locked Loop (Pll)  Voltage-controlled Oscillator (Vco)  Voltage-to-current Converter (Vic)  
A flooding warning system based on RFID tag array for energy facility Conference paper
RFID-TA 2018 - 2018 IEEE International Conference on RFID Technology and Applications, Macau, Macao, 26-28 Sept. 2018
Authors:  Chang-He Li;  Keng-Weng Lao;  Kam-Weng Tam
Favorite |  | TC[WOS]:0 TC[Scopus]:2 | Submit date:2019/02/13
Buried  Passive Rfid Tags  Rfid  Rssi  Signal Strength