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A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC Journal article
IEEE Journal of Solid-State Circuits, 2020
Authors:  Song,Yan;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
Analog-to-digital converter (ADC)  Calibration  Capacitors  Gain  noise-shaping (NS)  offset calibration  Pipelines  Registers  successive approximation register (SAR)-assisted pipeline  System-on-chip  time interleaving.  Transfer functions  
A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 12,Page: 4850-4861
Authors:  Fan,Chao;  Yu,Wei Han;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:1 | Submit date:2021/03/09
CMOS  current-mode-logic (CML) driver  feed-forward equalization (FFE)  four-level pulse-amplitude modulation (PAM-4)  source-series-terminated (SST) driver  SST-CML-Hybrid (SCH) driver  transmitter (TX)  
A digital LDO with transient enhancement and limit cycle oscillation reduction Conference paper
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, South Korea, 25-28 Oct. 2016
Authors:  Mo Huang;  Yan Lu;  Seng-Pan U;  Rui P. Martins
Favorite |  | TC[WOS]:5 TC[Scopus]:3 | Submit date:2019/02/11
Low Dropout Regulator (Ldo)  Digital Control  Coarse-fine-tuning (Cft)  Burst-mode  Limit Cycle Oscillation (Lco)  Feed-forward Path  Compensation Zero