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A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 6,Page: 2307-2316
Authors:  Yang, Zunsong;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
CMOS  current-reuse sampling phase detector (CRS-PD)  integrated jitter  loop filter (LF)  master-slave sampling filter (MSSF)  master-slave sampling phase detector (MSS-PD)  phase noise (PN)  Phase-locked loop (PLL)  reference spur  ring voltage-controlled oscillator (VCO)  type-I  type-II  
A 6.78-MHz Single-Stage Regulating Rectifier with Hysteretic Control and Current-Wave Modulation Conference paper
2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020
Authors:  Lin,Jie;  Zhan,Chenchang;  Lu,Yan
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/11
Current-wave modulation  Hysteretic control  Load-transient response  Regulating rectifier  Wireless power transfer (WPT)  
Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 3965-3977
Authors:  Martins,Ricardo;  Lourenco,Nuno;  Horta,Nuno;  Zhong,Shenke;  Yin,Jun;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:3 | Submit date:2021/03/04
Automatic layout generation  electronic design automation  multi-objective optimization  nanometer CMOS  ultralow-power  voltage-controlled oscillator  
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS Conference paper
Proceedings of the Custom Integrated Circuits Conference
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/03/04
acquisition speed  Alexander phase detector (PD)  bang-bang  bang-bang clock and data recovery (CDR)  charge pump (CP)  frequency detector (FD)  full-rate  jitter tolerance (JTF)  jitter transfer function (JTF)  Single loop  strobe point (SP)  
A 0.096-mm2 1-20-GHz triple-path noise- canceling common-gate common-source LNA with dual complementary pMOS-nMOS configuration Journal article
IEEE Transactions on Microwave Theory and Techniques, 2020,Volume: 68,Issue: 1,Page: 144-159
Authors:  Yu,Haohong;  Chen,Yong;  Boon,Chirn Chye;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:12 TC[Scopus]:15 | Submit date:2021/03/09
CMOS  common gate (CG)  common source (CS)  input third-order intercept point (IIP3)  noise figure (NF)  partial distortion canceling  pMOS-nMOS configuration  resistive feedback  triple-path and dual-path noise canceling (NC)  wideband input matching  wideband low-noise amplifier (LNA)  
A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 12,Page: 4850-4861
Authors:  Fan,Chao;  Yu,Wei Han;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:1 | Submit date:2021/03/09
CMOS  current-mode-logic (CML) driver  feed-forward equalization (FFE)  four-level pulse-amplitude modulation (PAM-4)  source-series-terminated (SST) driver  SST-CML-Hybrid (SCH) driver  transmitter (TX)  
A 0.003-mm2 440fsRMS-Jitter and-64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Conference paper
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:5 | Submit date:2021/03/09
phase detector  phase locked loop (PLL)  reference spur  Ring voltage-controlled oscillator (VCO)  RMS jitter  
A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 10,Page: 3991-4004
Authors:  Chen,Yong;  Mak,Pui In;  Yang,Zunsong;  Boon,Chirn Chye;  Martins,Rui P.
Favorite |  | TC[WOS]:5 TC[Scopus]:5 | Submit date:2021/03/09
active inductor (AI)  bandwidth (BW) extension  CMOS  current reuse  current-mode logic (CML)  current-mode transmitter  data-dependent jitter (DDJ)  figure-of-merit (FOM)  flip-flop (FF)  Fractional de-emphasis (DE)  hybrid delay line  latch  pulse-width-modulated (PWM)  unit interval (UI)  
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 9,Page: 3307-3316
Authors:  Un,Ka Fai;  Qi,Gengzhen;  Yin,Jun;  Yang,Shiheng;  Yu,Shupeng;  Ieong,Chio In;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:3 | Submit date:2021/03/09
bang-bang  Digital phase-locked loop (DPLL)  digital-to-time converter (DTC)  gain calibration  ring VCO  ultra-fast settling  ultra-low-power (ULP)  voltage-controlled oscillator (VCO)  
A 6.5 ×7μ m2 0.98-to-1.5 mW Nonself-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4-44 GHz) Journal article
IEEE Solid-State Circuits Letters, 2019,Volume: 2,Issue: 5,Page: 37-40
Authors:  Chen,Yong;  Yang,Zunsong;  Zhao,Xiaoteng;  Huang,Yunbo;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:8 | Submit date:2021/03/09
5G bands  current-mode-logic (CML)  figure-of-merit (FOM)  frequency divider  locking range (LR)  non-self-oscillation-mode (NSOM)  phasor  self-oscillation-mode (SOM)