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A Two-Phase Three-Level Buck Converter with Cross-Connected Flying Capacitors for Inductor Current Balancing Journal article
IEEE Transactions on Power Electronics, 2021,Volume: 36,Issue: 12,Page: 13855-13866
Authors:  Wang, Chuang;  Lu, Yan;  Huang, Mo;  Martins, Rui
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Buck converter  cross-connected  current balancing  electromagnetic interference  envelope tracking  interconnected  two-phase three-level converter (2P3L)  
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3108-3112
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In;  Li, Qiang;  Martins, Rui P.
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analog phase-locked loop (PLL)  Area  charge-sharing integrator  CMOS  digital PLL  hybrid PLL  integer-N  integrator  jitter  ring oscillator  ultra-low power  
A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3093-3097
Authors:  Huang, Yunbo;  Chen, Yong;  Jiao, Hailong;  Mak, Pui In;  Martins, Rui P.
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CMOS  narrow pulse shielding  reference (REF) feedthrough suppression  sampling phase-locked loop (S-PLL)  T-shape switch  type-I  voltage-controlled oscillator (VCO)  
Adaptive Maximum Power Point Tracking with Model-Based Negative Feedback Control and Improved V-f Model Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3103-3107
Authors:  Wang, Yuanfei;  Huang, Mo;  Luo, Ping;  Lu, Yan;  Martins, Rui P.
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energy harvesting system~(EHS)  maximum input power point tracking (MIPPT)  maximum output power point tracking (MOPPT)  Model-based method  NFC-based MPPT  
A 2.4-GHz CMOS Differential Class-DE Rectifier with Coupled Inductors Journal article
IEEE Transactions on Power Electronics, 2021,Volume: 36,Issue: 9,Page: 9864-9875
Authors:  Hu, Tingxu;  Huang, Mo;  Lu, Yan;  Zhang, Xiu Yin;  Maloberti, Franco;  Martins, Rui
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Class-DE rectifier  CMOS differential rectifier  coupled inductors  radio frequency (RF)  wireless power transfer (WPT)  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
IEEE Journal of Solid-State Circuits, 2021,Volume: 56,Issue: 8,Page: 2375-2387
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
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Analog-to-digital converter (ADC)  data weighting average (DWA)  delta-sigma modulator (DSM)  digital bank filters  digital-to-analog converter (DAC)  discrete-time (DT)  dithering  dynamic element matching (DEM)  extrapolation  noise-coupling  time-domain analysis  time-interleaved (TI)  
A Time-Domain CMOS Temperature Sensor Using Gated Ring Oscillator with Linearity Optimization Conference paper
ISSCS 2021 - International Symposium on Signals, Circuits and Systems
Authors:  Liu, Yangyang;  Lei, Yu;  Law, Man Kay;  Veigas, Bruno;  Mak, Pui In;  Martins, Rui P.
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BJT  CMOS temperature sensor  Gated ring oscillator  Linearity optimization  Time domain  
A highly integrated 3-phase 4:1 Resonant switched-capacitor converter with parasitic loss reduction and fast pre-charge startup Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 7,Page: 2608-2612
Authors:  Wang, Chuang;  Lu, Yan;  Martins, Rui P.
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3-phase operation  DC-DC converter  highly-integrated  resonant switched-capacitor converter  
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4thNyquist Zone in 1GS/s ADC Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Wei, Lai;  Zheng, Zihao;  Markulic, Nereo;  Lagos, Jorge;  Martens, Ewout;  Zhu, Yan;  Chan, Chi Hang;  Craninckx, Jan;  Martins, Rui Paulo
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Background calibration  nonlinearity  pipelined ADC  split-SAR ADC  
A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS Conference paper
Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Wang, Lin;  Mak, Pui In;  Maloberti, Franco;  Martins, Rui P.
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4-level pulse amplitude modulation (PAM-4)  Bang-bang clock and data recovery (BBCDR)  Charge pump (CP)  CMOS  Frequency detector (FD)  Half-rate  Negative (NNC) net current  Positive (PNC)  Reference less  Single loop  Zero (ZNC)