UM

Browse/Search Results:  1-10 of 193 Help

Selected(0)Clear Items/Page:    Sort:
A 4-bit Mixed-Signal MAC Array with Swing Enhancement and Local Kernel Memory Conference paper
Midwest Symposium on Circuits and Systems, Lansing, MI, USA, 13 September 2021
Authors:  Yu, Wei Han;  Giordano, Massimo;  Doshi, Rohan;  Zhang, Minglei;  Mak, Pui In;  Martins, Rui P.;  Murmann, Boris
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/10/28
Deep Neural Networks  Hardware Accelerators  In-memory Computing  Mixed-signal Integrated Circuits  Switched Capacitor Circuits  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
IEEE Journal of Solid-State Circuits, 2021,Volume: 56,Issue: 8,Page: 2375-2387
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Analog-to-digital converter (ADC)  data weighting average (DWA)  delta-sigma modulator (DSM)  digital bank filters  digital-to-analog converter (DAC)  discrete-time (DT)  dithering  dynamic element matching (DEM)  extrapolation  noise-coupling  time-domain analysis  time-interleaved (TI)  
A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array Journal article
Microelectronics Journal, 2021,Volume: 113
Authors:  Dong, Li;  Song, Yan;  Xie, Yi;  Xin, Youze;  Li, Ken;  Jing, Xixin;  Zhang, Bing;  Gui, Xiaoyan;  Geng, Li
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/12/08
Analog-to-digital converter (ADC)  Area-efficient  DAC mismatch  High linearity  Insensitive geometry  
A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Zhang, Minglei;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Background  input independent  time domain ADC  time-interleaved ADC  timing skew calibration  
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4thNyquist Zone in 1GS/s ADC Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Wei, Lai;  Zheng, Zihao;  Markulic, Nereo;  Lagos, Jorge;  Martens, Ewout;  Zhu, Yan;  Chan, Chi Hang;  Craninckx, Jan;  Martins, Rui Paulo
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Background calibration  nonlinearity  pipelined ADC  split-SAR ADC  
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS Journal article
IEEE Access, 2021,Volume: 9,Page: 77545-77554
Authors:  Li, Manxin;  Yao, Yuting;  Hu, Biao;  Wei, Jipeng;  Chen, Yong;  Ma, Shunli;  Ye, Fan;  Ren, Junyan
Favorite |  | TC[WOS]:1 TC[Scopus]:0 | Submit date:2021/10/28
Asynchronous Logic  Cmos  Customized Unit Capacitor  Figure-of-merit (Fom)  Split-cdac  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  
A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture Conference paper
Proceedings of the Custom Integrated Circuits Conference
Authors:  Zhang, Yanbo;  Zhang, Jin;  Liu, Shubin;  Zhu, Zhangming;  Zhu, Yan;  Chan, Chi Hang;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
A Dual-Loop 4-Phase Switching LDO with Scalable Load Capability and Tunable Active Voltage Positioning for Microprocessors Conference paper
Proceedings of the Custom Integrated Circuits Conference
Authors:  Mao, Xiangyu;  Lu, Yan;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, ELECTR NETWORK, FEB 13-22, 2021
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Chan, Chi Hang;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 2,Page: 557-568
Authors:  Jiang,Wenning;  Zhu,Yan;  Chan,Chi Hang;  Murmann,Boris;  Martins,Rui Paulo
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2021/03/04
Analog-to-digital converter  background timing skew calibration  current integrating sampler  SAR ADC  time-interleaved ADC  timing skew