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A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3108-3112
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In;  Li, Qiang;  Martins, Rui P.
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analog phase-locked loop (PLL)  Area  charge-sharing integrator  CMOS  digital PLL  hybrid PLL  integer-N  integrator  jitter  ring oscillator  ultra-low power  
A 4-bit Mixed-Signal MAC Array with Swing Enhancement and Local Kernel Memory Conference paper
Midwest Symposium on Circuits and Systems, Lansing, MI, USA, 13 September 2021
Authors:  Yu, Wei Han;  Giordano, Massimo;  Doshi, Rohan;  Zhang, Minglei;  Mak, Pui In;  Martins, Rui P.;  Murmann, Boris
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Deep Neural Networks  Hardware Accelerators  In-memory Computing  Mixed-signal Integrated Circuits  Switched Capacitor Circuits  
A 1.55-to-32-gb/s four-lane transmitter with 3-tap feed forward equalizer and shared pll in 28-nm cmos Journal article
Electronics (Switzerland), 2021,Volume: 10,Issue: 16
Authors:  Cai, Chen;  Zheng, Xuqiang;  Chen, Yong;  Wu, Danyu;  Luan, Jian;  Lu, Dechao;  Zhou, Lei;  Wu, Jin;  Liu, Xinyu
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CMOS  Feed-forward equalizer (FFE)  High-speed serial interface  Phase-locked loop (PLL)  Transmitter (TX)  Voltage-controlled oscillator (VCO)  
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4thNyquist Zone in 1GS/s ADC Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Wei, Lai;  Zheng, Zihao;  Markulic, Nereo;  Lagos, Jorge;  Martens, Ewout;  Zhu, Yan;  Chan, Chi Hang;  Craninckx, Jan;  Martins, Rui Paulo
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Background calibration  nonlinearity  pipelined ADC  split-SAR ADC  
A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS Conference paper
Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Wang, Lin;  Mak, Pui In;  Maloberti, Franco;  Martins, Rui P.
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4-level pulse amplitude modulation (PAM-4)  Bang-bang clock and data recovery (BBCDR)  Charge pump (CP)  CMOS  Frequency detector (FD)  Half-rate  Negative (NNC) net current  Positive (PNC)  Reference less  Single loop  Zero (ZNC)  
A Dual-Loop 4-Phase Switching LDO with Scalable Load Capability and Tunable Active Voltage Positioning for Microprocessors Conference paper
Proceedings of the Custom Integrated Circuits Conference
Authors:  Mao, Xiangyu;  Lu, Yan;  Martins, Rui P.
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A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 2,Page: 557-568
Authors:  Jiang,Wenning;  Zhu,Yan;  Chan,Chi Hang;  Murmann,Boris;  Martins,Rui Paulo
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2021/03/04
Analog-to-digital converter  background timing skew calibration  current integrating sampler  SAR ADC  time-interleaved ADC  timing skew  
Wideband variable-gain amplifiers based on a pseudo-current-steering gain-tuning technique Journal article
IEEE Access, 2021,Volume: 9,Page: 35814-35823
Authors:  Kong, Lingshan;  Chen, Yong;  Yu, Haohong;  Boon, Chirn Chye;  Mak, Pui In;  Martins, Rui P.
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active inductor  CMOS  data-dependent jitter (DDJ)  dual-branch current mirror  high-speed transceiver  negative capacitance (NC)  peak-to-peak jitter  pseudo-current steering  variable-gain amplifier (VGA)  wide-tuning gain control  
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS Journal article
IEEE Access, 2021,Volume: 9,Page: 77545-77554
Authors:  Li, Manxin;  Yao, Yuting;  Hu, Biao;  Wei, Jipeng;  Chen, Yong;  Ma, Shunli;  Ye, Fan;  Ren, Junyan
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asynchronous logic  CMOS  customized unit capacitor  figure-of-merit (FoM)  split-CDAC  Successive approximation register (SAR) analog-to-digital converter (ADC)  
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2021
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/10/28
Acquisition speed  bang-bang clock and data recovery (BBCDR)  charge pump (CP)  Clocks  CMOS  Detectors  four-level pulse amplitude modulation (PAM-4)  frequency detector (FD)  Frequency modulation  hybrid control circuit (HCC)  Jitter  jitter tolerance (JTOL)  jitter transfer function (JTF)  Logic gates  phase detector (PD)  strobe point (SP).  Switches  Voltage-controlled oscillators