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| Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015,Volume: 62,Issue: 9,Page: 2196-2206
Authors: Jianyu Zhong; Yan Zhu ; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins
  Favorite | | TC[WOS]:16 TC[Scopus]:16 | Submit date：2019/02/11
Analog-to-digital Converter (Adc) Reference Noise Successive-approximation-register (Sar) Adc Thermal Noise |
| A background gain-calibration technique for low voltage pipelined ADCs based on nonlinear interpolation Conference paper
2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, USA, 4-7 Aug. 2013
Authors: Li Ding; Sai-Weng Sin; Seng-Pan U; R.P.Martins
Favorite | | TC[WOS]:1 TC[Scopus]:1 | Submit date：2019/02/11
Digital Calibration Lms Algorithm Nonlinear Interpolation Pipelined Adcs |
| A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC Conference paper
2012 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, USA, 13-15 June 2012
Authors: Yan Zhu; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; R.P.Martins
Favorite | | TC[WOS]:0 TC[Scopus]:29 | Submit date：2019/02/11 |
| A nonlinearity digital background calibration algorithm for 2.5bit/stage pipelined ADCs with opamp sharing architecture Conference paper
Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Macau, China, 6-7 Oct. 2011
Authors: Fei Y.; Sin S.-W.; Seng-Pan U.; Martins R.P.
Favorite | | TC[WOS]:0 TC[Scopus]:0 | Submit date：2019/02/11 |
| A digital background nonlinearity calibration algorithm for pipelined ADCs Conference paper
PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Shanghai, China, 22-24 Sept. 2010
Authors: Fei Y.; Sin S.-W.; U S.-P.; Martins R.P.
Favorite | | TC[WOS]:0 TC[Scopus]:1 | Submit date：2019/02/11 |
| An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs Conference paper
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, Kuala Lumpur, MALAYSIA, DEC 06-09, 2010
Authors: Li D.; Sin S.-W.; Seng-Pan U.; Martins R.P.
Favorite | | TC[WOS]:2 TC[Scopus]:3 | Submit date：2019/02/11
Capacitor Mismatch Digital Calibration Interstage Gain Error Pipelined Adcs |
| A background amplifier offset calibration technique for high-resolution pipelined ADCs Conference paper
Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010, Montreal, QC, Canada, 20-23 June 2010
Authors: Ding L.; Sin S.-W.; U S.-P.; Martins R.P.
Favorite | | TC[WOS]:0 TC[Scopus]:2 | Submit date：2019/02/11 |
| A 1.2-V 10-bit 60–360MS/s Time-Interleaved Pipelined ADC in 0.18μm CMOS with Minimized Supply Headroom Journal article
IET Circuits, Devices & Systems, 2010,Volume: 4,Issue: 1,Page: 1-13
Authors: S.-W. Sin; Seng-Pan U; R.P. Martins
Favorite | | TC[WOS]:8 TC[Scopus]:0 | Submit date：2019/03/14 |
| 1.2-V, 10-bit, 60– 360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 mm CMOS with minimised supply headroom Journal article
IET Circuits, Devices & Systems, 2010,Volume: 4,Issue: 1,Page: 1-13
Authors: S.-W. Sin; Seng-Pan U; R.P. Martins
Favorite | | TC[WOS]:8 TC[Scopus]:0 | Submit date：2019/02/27 |
| A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18 um CMOS Journal article
澳門機電工程專業協會(APEMEM)會刊, 2009
Authors: Sai-Weng Sin; Seng-Pan U; R.P.Martins
Favorite | | TC[WOS]:0 TC[Scopus]:0 | Submit date：2019/02/28
Index Terms-pipelined Adc Low-voltage Current-mode Comparator |
