UM
(Note: the search results are based on claimed items)

Browse/Search Results:  1-2 of 2 Help

Filters        
Selected(0)Clear Items/Page:    Sort:
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 1,Page: 354-363
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Pan, Seng U.;  Martins, Rui Paulo
Favorite |  | TC[WOS]:8 TC[Scopus]:8 | Submit date:2018/10/30
Offset Calibration  Partial Interleaving (Pi)  Pipelined-sar  Stage-gain Error Calibration  
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC Conference paper
2012 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, USA, 13-15 June 2012
Authors:  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite |  | TC[WOS]:0 TC[Scopus]:29 | Submit date:2019/02/11