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A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Zheng,Zihao;  Wei,Lai;  Lagos,Jorge;  Martens,Ewout;  Zhu,Yan;  Chan,Chi Hang;  Craninckx,Jan;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:2 | Submit date:2021/03/04
3.2 A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Jiang,Wenning;  Zhu,Yan;  Zhang,Minglei;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:9 | Submit date:2021/03/09
A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Conference paper
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Zheng, Zi-Hao;  Li, Cheng;  Zhong, Jian-Yu;  Martins, Rui P.
Favorite |  | TC[WOS]:4 TC[Scopus]:4 | Submit date:2018/10/30
Time-interleaved ADC  sampling front-end design  passive sharing  pipelined-SAR ADC  switch bootstrap technique  
A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current Conference paper
Authors:  Mao, Jiaji;  Guo, Mingqiang;  Sin, Sai-Weng;  Martins, Rui Paulo
Favorite |  | TC[WOS]:3 TC[Scopus]:4 | Submit date:2018/10/30
Analog-to-digital conversion  digital background calibration  pipelined ADC  split ADC  opamp-sharing technique  
A background gain-calibration technique for low voltage pipelined ADCs based on nonlinear interpolation Conference paper
2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, USA, 4-7 Aug. 2013
Authors:  Li Ding;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2019/02/11
Digital Calibration  Lms Algorithm  Nonlinear Interpolation  Pipelined Adcs  
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC Conference paper
2012 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, USA, 13-15 June 2012
Authors:  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite |  | TC[WOS]:0 TC[Scopus]:29 | Submit date:2019/02/11
A nonlinearity digital background calibration algorithm for 2.5bit/stage pipelined ADCs with opamp sharing architecture Conference paper
Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Macau, China, 6-7 Oct. 2011
Authors:  Fei Y.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11
A digital background nonlinearity calibration algorithm for pipelined ADCs Conference paper
PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Shanghai, China, 22-24 Sept. 2010
Authors:  Fei Y.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2019/02/11
An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs Conference paper
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, Kuala Lumpur, MALAYSIA, DEC 06-09, 2010
Authors:  Li D.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:2 TC[Scopus]:3 | Submit date:2019/02/11
Capacitor Mismatch  Digital Calibration  Interstage Gain Error  Pipelined Adcs  
A background amplifier offset calibration technique for high-resolution pipelined ADCs Conference paper
Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010, Montreal, QC, Canada, 20-23 June 2010
Authors:  Ding L.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:2 | Submit date:2019/02/11