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An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs Conference paper
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, Kuala Lumpur, MALAYSIA, DEC 06-09, 2010
Authors:  Li D.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:2 TC[Scopus]:3 | Submit date:2019/02/11
Capacitor Mismatch  Digital Calibration  Interstage Gain Error  Pipelined Adcs