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A 1.55-to-32-gb/s four-lane transmitter with 3-tap feed forward equalizer and shared pll in 28-nm cmos
Cai, Chen1; Zheng, Xuqiang1; Chen, Yong2; Wu, Danyu1; Luan, Jian1; Lu, Dechao1; Zhou, Lei1; Wu, Jin1; Liu, Xinyu1
2021-08-02
Source PublicationElectronics (Switzerland)
ISSN2079-9292
Volume10Issue:16
Abstract

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm. The shared PLL and clock distribution circuits occupied an area of 0.54 mm. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

KeywordCmos Feed-forward Equalizer (Ffe) High-speed Serial Interface Phase-locked Loop (Pll) Transmitter (Tx) Voltage-controlled Oscillator (Vco)
DOI10.3390/electronics10161873
URLView the original
Indexed BySCIE
Language英語English
WOS Research AreaComputer Science ; Engineering ; Physics
WOS SubjectComputer Science, Information Systems ; Engineering, Electrical & Electronic ; Physics, Applied 2.397
WOS IDWOS:000688820000001
Scopus ID2-s2.0-85111756888
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Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
Corresponding AuthorZheng, Xuqiang
Affiliation1.Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, China
2.State-Key Laboratory of Analog and Mixed-Signal VLSI/IME and the DECE/Faculty of Science and Technology, University of Macau, Macau, 999078, China
Recommended Citation
GB/T 7714
Cai, Chen,Zheng, Xuqiang,Chen, Yong,et al. A 1.55-to-32-gb/s four-lane transmitter with 3-tap feed forward equalizer and shared pll in 28-nm cmos[J]. Electronics (Switzerland),2021,10(16).
APA Cai, Chen,Zheng, Xuqiang,Chen, Yong,Wu, Danyu,Luan, Jian,Lu, Dechao,Zhou, Lei,Wu, Jin,&Liu, Xinyu.(2021).A 1.55-to-32-gb/s four-lane transmitter with 3-tap feed forward equalizer and shared pll in 28-nm cmos.Electronics (Switzerland),10(16).
MLA Cai, Chen,et al."A 1.55-to-32-gb/s four-lane transmitter with 3-tap feed forward equalizer and shared pll in 28-nm cmos".Electronics (Switzerland) 10.16(2021).
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