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A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-distorter (DAAPD) Reconfigurable Linearization Technique
Mariappan, Selvakumar1; Rajendran, Jagadheswaran2; Chen, Yong3; Mak, Pui In3; Martins, Rui P.4
2021-11
Source PublicationIEEE Transactions on Circuits and Systems II: Express Briefs
ISSN1549-7747
Volume68Issue:11Pages:3381-3385
Abstract

This brief presents a CMOS power amplifier (PA) employing a digitally-assisted analog pre-distorter (DAAPD) reconfigurable linearization technique to reduce the back-off output power (PBO) for multiband operation. The proposed DAAPD optimizes the interstage load impedance between the driver and the main stage by changing the transconductance of the driver amplifier and its active load.We also utilize the DAAPD to optimize the PA when subjected to process-voltagetemperature (PVT) variations. Fabricated in 130-nm CMOS, the DAAPDPA operates from 1.7 to 2.7 GHz with a 3 dB back-off output power efficiency of 35% to 38% while fulfilling the stringent adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) requirements of a 20-MHz 16-QAM LTE signal. With a continuous wave (CW) signal, the DAAPD-PA achieves a maximum output power of 27 to 28 dBm across frequencies of interest with supply headroom of 3.3 V. Finally, the DAAPD-PA covers 20 LTE bands with reduced back-off output power.

KeywordAdjacent Channel Leakage Ratio (Aclr) And Error Vector Magnitude (Evm) Back-off Output Power (Pbo) Cmos Digitally-assisted Analog Predistorter (Daapd) Long Term Evolution Long-term Evolution (Lte). Power Amplifier (Pa) Power Amplifiers Power Generation Power-added Efficiency (Pae) Transconductance Transistors Tuning Voltage Control
DOI10.1109/TCSII.2021.3080831
URLView the original
Indexed BySCIE
Language英語English
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000711728300004
Scopus ID2-s2.0-85107204165
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Cited Times [WOS]:0   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
Corresponding AuthorRajendran, Jagadheswaran
Affiliation1.Collaborative Microelectronic Design Excellence Centre (CEDEC), Engineering Campus, Universiti Sains Malaysia, Penang, Malaysia.
2.Collaborative Microelectronic Design Excellence Centre (CEDEC), Engineering Campus, Universiti Sains Malaysia, Penang, Malaysia. (e-mail: jaga.rajendran@usm.my)
3.State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST, University of Macau, Macao, China.
4.State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST, University of Macau, Macao, China, also with leave from Instituto Superior Técnico, Universidade de Lisboa, Portugal.
Recommended Citation
GB/T 7714
Mariappan, Selvakumar,Rajendran, Jagadheswaran,Chen, Yong,et al. A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-distorter (DAAPD) Reconfigurable Linearization Technique[J]. IEEE Transactions on Circuits and Systems II: Express Briefs,2021,68(11):3381-3385.
APA Mariappan, Selvakumar,Rajendran, Jagadheswaran,Chen, Yong,Mak, Pui In,&Martins, Rui P..(2021).A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-distorter (DAAPD) Reconfigurable Linearization Technique.IEEE Transactions on Circuits and Systems II: Express Briefs,68(11),3381-3385.
MLA Mariappan, Selvakumar,et al."A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-distorter (DAAPD) Reconfigurable Linearization Technique".IEEE Transactions on Circuits and Systems II: Express Briefs 68.11(2021):3381-3385.
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