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A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS
Zhao, Xiaoteng1; Chen, Yong1; Wang, Lin1; Mak, Pui In1; Maloberti, Franco2; Martins, Rui P.3
2021-07
Conference Name2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Source PublicationDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Volume2021-June
Pages131-134
Conference Date7-9 June 2021
Conference PlaceAtlanta, GA, USA
Abstract

This paper reports a reference-less single-loop bang-bang clock and data recovery (BBCDR) circuit featuring fast and robust frequency acquisition without identifying the frequency error polarity. The key idea is a deliberately-current-mismatch charge-pump pair, which avoids the need of a complex high-speed data path or clock path during frequency acquisition. Prototyped in 28nm CMOS, our BBCDR covers a 47.6-to-58.8Gb/s PAM-4 input automatically. The achieved energy efficiency (≤0.25pJ/bit) and acquisition speed $[9.8(\text{Gb}/\mathrm{s})/\mu\mathrm{s}]$ compare favorably with the prior art. Keywords - CMOS, reference less, single loop, half-rate, bang-bang clock and data recovery (BBCDR), frequency detector (FD), charge pump (CP), 4-level pulse amplitude modulation (PAM-4), zero (ZNC), positive (PNC), and negative (NNC) net current.

Keyword4-level Pulse Amplitude Modulation (Pam-4) Bang-bang Clock And Data Recovery (Bbcdr) Charge Pump (Cp) Cmos Frequency Detector (Fd) Half-rate Negative (Nnc) Net Current Positive (Pnc) Reference Less Single Loop Zero (Znc)
DOI10.1109/RFIC51843.2021.9490486
URLView the original
Language英語English
Scopus ID2-s2.0-85111755307
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Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Affiliation1.State Key Laboratory of Analog and Mixed-Signal VLSI, IME/FST-ECE, University of Macau, Macao
2.University of Pavia, Pavia, 27100, Italy
3.On Leave from Instituto Superior Técnico, Universidade de Lisboa, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Zhao, Xiaoteng,Chen, Yong,Wang, Lin,et al. A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS[C],2021:131-134.
APA Zhao, Xiaoteng,Chen, Yong,Wang, Lin,Mak, Pui In,Maloberti, Franco,&Martins, Rui P..(2021).A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS.Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium,2021-June,131-134.
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