UM
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation
Jiang, Dongyang1,3; Qi, Liang1,4; Sin, Sai Weng1; Maloberti, Franco2,5; Martins, Rui P.1,3,6
2021-08-01
Source PublicationIEEE Journal of Solid-State Circuits
ISSN0018-9200
Volume56Issue:8Pages:2375-2387
AbstractThis article presents a $4\times $ time-interleaved (TI) 2nd-order discrete-time (DT) delta-sigma modulator (DSM). We propose a digital feed-forward extrapolation by first digitizing the internal analog nodes' information from one channel, and then extrapolating the other channels in the digital domain. As a result, this DSM only needs two operational amplifiers (op-amps) to realize four interleaving paths, thus reducing analog hardware overheads. Meanwhile, we linearize the digital feed-forward paths through injected dithering. We present the derivation of extrapolating TI DSM starting from a single-channel DSM, while we also list and compare several conventional TI approaches. Implemented in 28-nm CMOS, this modulator achieves an equivalent output-sampling rate of 2.08 GS/s, $208\times $ oversampling ratio (OSR), and a signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 86.1 dB/98 dB with 5-MHz bandwidth (BW). The power consumption is 23.1 mW, which results in a Schreier Figure of Merit (FoM) of 169.5 dB.
KeywordAnalog-to-digital converter (ADC) data weighting average (DWA) delta-sigma modulator (DSM) digital bank filters digital-to-analog converter (DAC) discrete-time (DT) dithering dynamic element matching (DEM) extrapolation noise-coupling time-domain analysis time-interleaved (TI)
DOI10.1109/JSSC.2021.3060859
URLView the original
Language英語English
Scopus ID2-s2.0-85102639566
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Document TypeJournal article
CollectionUniversity of Macau
Affiliation1.State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macao
2.State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao
3.Department of ECE, Faculty of Science and Technology, University of Macau, 999078, Macao
4.Department of Micro/Nano Electronics, Shanghai Jiao Tong University, Shanghai, 200240, China
5.Department of Electronics, The University of Pavia, Pavia, 27100, Italy
6.Instituto Superior Técnico, Universidade de Lisboa, Lisbon, 1049-001, Portugal
First Author AffilicationUniversity of Macau;  Faculty of Science and Technology
Recommended Citation
GB/T 7714
Jiang, Dongyang,Qi, Liang,Sin, Sai Weng,et al. A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation[J]. IEEE Journal of Solid-State Circuits,2021,56(8):2375-2387.
APA Jiang, Dongyang,Qi, Liang,Sin, Sai Weng,Maloberti, Franco,&Martins, Rui P..(2021).A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation.IEEE Journal of Solid-State Circuits,56(8),2375-2387.
MLA Jiang, Dongyang,et al."A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation".IEEE Journal of Solid-State Circuits 56.8(2021):2375-2387.
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