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A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS
Yang, Shiheng; Yin, Jun; Xu, Tailong; Yi, Taimo; Mak, Pui In; Li, Qiang; Martins, Rui P.
2021-09-01
Source PublicationIEEE Transactions on Circuits and Systems II: Express Briefs
ISSN1549-7747
Volume68Issue:9Pages:3108-3112
AbstractThis brief presents a hybrid PLL by leveraging the advantages of analog and digital techniques in the frequency-control loop to achieve ultra-compact area and ultra-low power consumption simultaneously. Specifically, the hybrid loop consists of two paths: an integral path features a charge-sharing integrator realized by switched capacitors with high precision in digital discrete integration to improve the frequency resolution without deteriorating the output phase noise, and a proportional path directly switches the bias voltage of the VCO varactors to compensate the phase margin without costing extra power and area. Both paths are digitally controlled by a tiny power-efficient 1-bit bang-bang phase detector (BBPD). Prototyped in 28-nm CMOS, the 1.3-to-2.3-GHz PLL occupies a core area of 600 \mu \text{m}~^{2} and dissipates 380 \mu \text{W} at a 0.8-V supply, of which only 30 \mu \text{W} is due to the hybrid loop. At a 2.0-GHz output, the PLL exhibits a reference spur of -60.5 dBc and a jitter of 1.71 ps _{rms} , resulting in state-of-the-art FoMR of -239.5 dB, and FoMNRA of -271.7 dB.
Keywordanalog phase-locked loop (PLL) Area charge-sharing integrator CMOS digital PLL hybrid PLL integer-N integrator jitter ring oscillator ultra-low power
DOI10.1109/TCSII.2021.3096193
URLView the original
Language英語English
Scopus ID2-s2.0-85110814800
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Document TypeJournal article
CollectionUniversity of Macau
AffiliationState-Key Laboratory of Analog and Mixed-Signal Vlsi, University of Macau, Macao
First Author AffilicationUniversity of Macau
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GB/T 7714
Yang, Shiheng,Yin, Jun,Xu, Tailong,et al. A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs,2021,68(9):3108-3112.
APA Yang, Shiheng,Yin, Jun,Xu, Tailong,Yi, Taimo,Mak, Pui In,Li, Qiang,&Martins, Rui P..(2021).A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS.IEEE Transactions on Circuits and Systems II: Express Briefs,68(9),3108-3112.
MLA Yang, Shiheng,et al."A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS".IEEE Transactions on Circuits and Systems II: Express Briefs 68.9(2021):3108-3112.
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