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A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques
Huang, Yunbo1; Chen, Yong1; Jiao, Hailong2; Mak, Pui In1; Martins, Rui P.1,3
2021-09-01
Source PublicationIEEE Transactions on Circuits and Systems II: Express Briefs
ISSN1549-7747
Volume68Issue:9Pages:3093-3097
Abstract

This brief describes a type-I analog sampling phase-locked loop (S-PLL) featuring reference-feedthrough-suppression and narrow-pulse-shielding techniques in a single path to improve the reference (REF) spur. Specifically, we realize the former by inserting a T-shape switch with one center-tap ground, while the latter tackles the voltage ripple caused by the sampling non-idealities. Also, we can tune an external varactor to eliminate both the gain variation of the phase detector and the gate leakage of the frequency-tuning varactor. Prototyped in a 28-nm CMOS, the proposed S-PLL achieves a -78.6-dBc REF spur and 124.6-fs integrated RMS jitter. The corresponding jitter-power Figure-of- Merit is -252.8 dB.

KeywordCmos Narrow Pulse Shielding Reference (Ref) Feedthrough Suppression Sampling Phase-locked Loop (S-pll) T-shape Switch Type-i Voltage-controlled Oscillator (Vco)
DOI10.1109/TCSII.2021.3094934
URLView the original
Indexed BySCIE ; CPCI-S
Language英語English
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000692209000016
Scopus ID2-s2.0-85114630775
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Cited Times [WOS]:3   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
Affiliation1.State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST, University of Macau, Macao
2.School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School, Nanshan, China
3.Instituto Superior Técnico, Universidade de Lisboa, Lisboa, 1049-001, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Huang, Yunbo,Chen, Yong,Jiao, Hailong,et al. A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques[J]. IEEE Transactions on Circuits and Systems II: Express Briefs,2021,68(9):3093-3097.
APA Huang, Yunbo,Chen, Yong,Jiao, Hailong,Mak, Pui In,&Martins, Rui P..(2021).A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques.IEEE Transactions on Circuits and Systems II: Express Briefs,68(9),3093-3097.
MLA Huang, Yunbo,et al."A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques".IEEE Transactions on Circuits and Systems II: Express Briefs 68.9(2021):3093-3097.
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