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A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis
Chen,Yong1,2; Mak,Pui In3; Yang,Zunsong1,2; Boon,Chirn Chye3; Martins,Rui P.4
2019-10-01
Source PublicationIEEE Transactions on Circuits and Systems I: Regular Papers
ISSN1549-8328
Volume66Issue:10Pages:3991-4004
AbstractThis paper proposes an ultra-compact 4 to 10-Gb/s 5-Tap current-mode transmitter to realize the sub 1-UI fractional de-emphasis (DE) using a hybrid delay line, which is alternatively controlled by the voltage bias and clock. It exhibits the scalability between the clocked 0.5-UI and 1-UI DEs and data rate. The sub-1-UI DE provides wide tunability of the data amplitude and delay to compensate different channel losses between the 1{st} and 2{nd} Nyquist frequencies while effectively compensating the high-frequency portion of the pseudo-random binary sequence (PRBS) spectrum for data jitter improvement. Additional techniques are a two-step current-summing scheme, namely, two-step DE in the data path, and active inductors in both the data and clock paths to enhance the internal bandwidth without the need for passive inductors. In addition, we present an analytical model for predicting data-dependent jitter (DDJ) based on a generic system's step response, derive the exact closed-form DDJ expression of DE, and verify its validity by mean of circuit simulation. Prototyped in 65-nm CMOS technology, it achieves a figure-of-merit of 4.6 mW/Gb/s and an output jitter of 10.8 ps at 10 Gb/s under a PRBS 2{31}-1 pattern. The data eyes measure 0.62-UI-horizontal and 19.5%-vertical openings after-20-dB channel loss. The die area is 0.0071 mm.
Keywordactive inductor (AI) bandwidth (BW) extension CMOS current reuse current-mode logic (CML) current-mode transmitter data-dependent jitter (DDJ) figure-of-merit (FOM) flip-flop (FF) Fractional de-emphasis (DE) hybrid delay line latch pulse-width-modulated (PWM) unit interval (UI)
DOI10.1109/TCSI.2019.2919623
URLView the original
Language英语
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Cited Times [WOS]:5   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
Corresponding AuthorChen,Yong
Affiliation1.State Key Laboratory of Analog and Mixed-Signal VLSI,University of Macau,Macao
2.Department of ECE,Faculty of Science and Technology,University of Macau,999078,Macao
3.Department of Electrical and Electronic Engineering,Nanyang Technological University,Singapore,Singapore
4.Instituto Superior Técnico,Universidade de Lisboa,Lisbon,1049-001,Portugal
First Author AffilicationUniversity of Macau;  Faculty of Science and Technology
Corresponding Author AffilicationUniversity of Macau;  Faculty of Science and Technology
Recommended Citation
GB/T 7714
Chen,Yong,Mak,Pui In,Yang,Zunsong,et al. A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis[J]. IEEE Transactions on Circuits and Systems I: Regular Papers,2019,66(10):3991-4004.
APA Chen,Yong,Mak,Pui In,Yang,Zunsong,Boon,Chirn Chye,&Martins,Rui P..(2019).A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis.IEEE Transactions on Circuits and Systems I: Regular Papers,66(10),3991-4004.
MLA Chen,Yong,et al."A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis".IEEE Transactions on Circuits and Systems I: Regular Papers 66.10(2019):3991-4004.
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