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A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector
Yang,Zunsong1,2; Chen,Yong1,2; Yang,Shiheng1,2; Mak,Pui In1,2; Martins,Rui P.1,2
2020
Source PublicationIEEE Access
Volume8Pages:2222-2232
AbstractThis paper reports a millimeter (mm)-wave type-II dual-loop phase-locked loop (PLL) with low-power and low-complexity design for improving jitter-power performance and power efficiency. Unlike the typical type-II single-loop PLL using a tri-state phase-frequency detector (PFD) plus a charge pump (CP) that has several limits in high-speed operation, our proposed PLL features a dual-loop scheme to enhance its performance and operating speed at low power. Specifically, we propose a dynamic frequency detector (FD) and a phase detector (PD) in conjunction with voltage-to-current converters (VICs) to avoid the typical current-mode-logic (CML) circuitry for static power reduction. Prototyped in 65-nm CMOS process, the entire PLL dissipates 10.6 mW, of which the dynamic FD and PD merely consume 0.28 mW. The integrated jitter is 415.6 fs (10 kHz to 100 MHz) and the reference spur level is -53 dBc at a 26.4-GHz output.
KeywordCMOS divider-by-4 dual loop dynamic latch figure-of-merit (FoM) frequency detector (FD) millimeter (mm)-wave phase detector (PD) phase-locked loop (PLL) voltage-controlled oscillator (VCO) voltage-to-current converter (VIC)
DOI10.1109/ACCESS.2019.2962060
URLView the original
Language英语
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Cited Times [WOS]:2   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
Corresponding AuthorChen,Yong
Affiliation1.State Key Laboratory of Analog and Mixed-Signal VLSI,University of Macau,999078,Macao
2.ECE,Faculty of Science and Technology,University of Macau,999078,Macao
First Author AffilicationUniversity of Macau;  Faculty of Science and Technology
Corresponding Author AffilicationUniversity of Macau;  Faculty of Science and Technology
Recommended Citation
GB/T 7714
Yang,Zunsong,Chen,Yong,Yang,Shiheng,et al. A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector[J]. IEEE Access,2020,8:2222-2232.
APA Yang,Zunsong,Chen,Yong,Yang,Shiheng,Mak,Pui In,&Martins,Rui P..(2020).A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector.IEEE Access,8,2222-2232.
MLA Yang,Zunsong,et al."A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector".IEEE Access 8(2020):2222-2232.
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