UM
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC
Song,Yan1; Zhu,Yan1; Chan,Chi Hang2; Martins,Rui P.3
2020
Source PublicationIEEE Journal of Solid-State Circuits
ISSN0018-9200
AbstractThis article presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipeline analog-to-digital converter (ADC) incorporating various techniques to improve its bandwidth (BW), energy efficiency, and robustness. A multiple-input dynamic amplifier is used for both residue amplification and error feedback (EF) summation, thus realizing a 1st-order NS with low power consumption. An additional residue feed-forward (FF) path is introduced in the 2nd-stage SAR ADC to compensate for the noise transfer function (NTF) deterioration caused by the gain mismatch in the multiple-input pairs of the dynamic amplifier. The partial-interleaving 1st stage breaks the speed bottleneck of the conventional three-phase timing arrangement, which significantly enhances the overall ADC's speed and sampling performance. Besides, a coarse SAR ADC is introduced to further speed up the conversion with low power, while simultaneously enabling the enclosure of the data-weighted-averaging (DWA) on the DAC without a speed penalty. Finally, a low-cost inter-stage offset calibration is proposed that aligns the offset voltages among stages in the background without requiring an extra phase. Fabricated in the 28-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 75.2 dB over 40-MHz BW with only 7.5 over-sampling rate (OSR). Under a 1-V supply voltage, the ADC consumes 2.56 mW and exhibits a Scherier figure-of-merit (FoM) of 177.1 dB.
KeywordAnalog-to-digital converter (ADC) Calibration Capacitors Gain noise-shaping (NS) offset calibration Pipelines Registers successive approximation register (SAR)-assisted pipeline System-on-chip time interleaving. Transfer functions
DOI10.1109/JSSC.2020.3033931
URLView the original
Language英语
Scopus ID2-s2.0-85098800702
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Document TypeJournal article
CollectionUniversity of Macau
Affiliation1.State Key Laboratory of Analog and Mixed Signal VLSI, Institute of Microelectronics, Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macao 999078, China.
2.State Key Laboratory of Analog and Mixed Signal VLSI, Institute of Microelectronics, Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macao 999078, China (e-mail: ivorchan@ieee.org)
3.State Key Laboratory of Analog and Mixed Signal VLSI, Institute of Microelectronics, Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macao 999078, China, on leave from Instituto Superior Técnico, Universidade de Lisboa, Lisbon 1649-004, Portugal.
First Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Song,Yan,Zhu,Yan,Chan,Chi Hang,et al. A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC[J]. IEEE Journal of Solid-State Circuits,2020.
APA Song,Yan,Zhu,Yan,Chan,Chi Hang,&Martins,Rui P..(2020).A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC.IEEE Journal of Solid-State Circuits.
MLA Song,Yan,et al."A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC".IEEE Journal of Solid-State Circuits (2020).
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