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A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance
Qi,Liang1,2; Jain,Ankesh3; Jiang,Dongyang1,2; Sin,Sai Weng1,2; Martins,Rui P.4,5; Ortmanns,Maurits6
2020-02-01
Source PublicationIEEE Journal of Solid-State Circuits
ISSN0018-9200
Volume55Issue:2Pages:344-355
AbstractThis article presents a dual-loop noise-coupling (NC)-assisted continuous-time (CT) sturdy multistage noise-shaping (SMASH) Δ Σ modulator (DSM), employing 1.5-bit/4-bit quantizers. The proposed SMASH can equivalently work as an overall fourth-order DSM with 4-bit internal quantization. The NC applied in this CT SMASH DSM whitens the 1.5-bit quantization noise (QN) and further reduces its in-band tone power, while a finite-impulse response (FIR) filter integrated into the outermost feedback path suppresses the out-of-band (OOB) noise power of the multibit digital-to-analog converter (DAC) input. Together, they avoid any linearization technique for the multibit DAC. Sampled at 1.2 GHz, the 28-nm CMOS experimental prototype measures a signal-to-noise-and-distortion ratio (SNDR) of 76.6 dB and a spurious-free dynamic range (SFDR) of 87.9 dB over a 50-MHz bandwidth (BW), consuming 29.2 mW from 1.2-V/1.5-V supplies and occupying an active area of 0.085 mm. It exhibits a Schreier figure-of-merit (FoM) (SNDR) of 168.9 dB.
KeywordAnalog-to-digital converter (ADC) continuous time (CT) digital-to-analog converter (DAC) linearization excess loop delay (ELD) compensation filter finite-impulse response (FIR) multibit quantization noise coupling (NC) sturdy multistage noise-shaping (SMASH) successive-approximation register (SAR)
DOI10.1109/JSSC.2019.2942359
URLView the original
Language英语
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Cited Times [WOS]:3   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
Affiliation1.State-Key Laboratory of Analog and Mixed-Signal VLSI,Institute of Microelectronics,University of Macau,999078,Macao
2.Department of Electrical and Computer Engineering,Faculty of Science and Technology,University of Macau,999078,Macao
3.Electrical Engineering Department,IIT Delhi,New Delhi,110016,India
4.Department of Electrical and Computer Engineering,University of Macau,State-Key Laboratory of Analog and Mixed-Signal VLSI,Institute of Microelectronics,Faculty of Science and Technology,999078,Macao
5.Instituto Superior Técnico,Universidade de Lisboa,Lisbon,1649-004,Portugal
6.Faculty of Engineering,Computer Science and Psychology,Institute of Microelectronics,University of Ulm,Ulm,89081,Germany
First Author AffilicationUniversity of Macau;  Faculty of Science and Technology
Recommended Citation
GB/T 7714
Qi,Liang,Jain,Ankesh,Jiang,Dongyang,et al. A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance[J]. IEEE Journal of Solid-State Circuits,2020,55(2):344-355.
APA Qi,Liang,Jain,Ankesh,Jiang,Dongyang,Sin,Sai Weng,Martins,Rui P.,&Ortmanns,Maurits.(2020).A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance.IEEE Journal of Solid-State Circuits,55(2),344-355.
MLA Qi,Liang,et al."A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance".IEEE Journal of Solid-State Circuits 55.2(2020):344-355.
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