UM
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration
Guo,Mingqiang1; Mao,Jiaji1; Sin,Sai Weng1; Wei,Hegong2; Martins,Rui P.1,3
2020-03-01
Source PublicationIEEE Journal of Solid-State Circuits
ISSN0018-9200
Volume55Issue:3Pages:693-705
AbstractThis article presents a split time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC) with digital background timing-skew mismatch calibration. It divides a TI-SAR ADC into two split parts with the same overall sampling rate but different numbers of TI channels. Benefitting from the proposed split TI topology, the timing-skew calibration convergence speed is fast without any extra analog circuits. The input impedance of the overall TI-ADC remains unchanged, which is essential for the preceding driving stage in a high-speed application. We designed a prototype seven-/eight-way split TI-ADC implemented in 28-nm CMOS. After a digital background timing-skew calibration, it reaches a 54.2-dB signal-to-noise-and-distortion ratio (SNDR) and 67.1-dB spurious free dynamic range (SFDR) with a near Nyquist rate input signal and a 2.5-GHz effective resolution bandwidth (ERBW). Furthermore, the power consumption of ADC core (mismatch calibration off-chip) is 12.2-mW running at 1.6 GS/s, leading to a Walden figure-of-merit (FOM) of 18.2 fJ/conv.-step and a Schreier FOM of 162.4 dB, respectively.
KeywordAnalog-to-digital converter (ADC) digital background calibration split ADC time-interleaved (TI) ADC timing-skew mismatch
DOI10.1109/JSSC.2019.2945298
URLView the original
Language英语
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Cited Times [WOS]:2   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
Affiliation1.State-Key Laboratory of Analog and Mixed-Signal VLSI,Institute of Microelectronics and Faculty of Science and Technology-ECE,University of Macau,Macao
2.Electrical and Computer Engineering Department,University of Texas at Austin,Austin,United States
3.Instituto Superior Tecnico,Universidade de Lisboa,Lisbon,1049-001,Portugal
First Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Guo,Mingqiang,Mao,Jiaji,Sin,Sai Weng,et al. A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration[J]. IEEE Journal of Solid-State Circuits,2020,55(3):693-705.
APA Guo,Mingqiang,Mao,Jiaji,Sin,Sai Weng,Wei,Hegong,&Martins,Rui P..(2020).A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration.IEEE Journal of Solid-State Circuits,55(3),693-705.
MLA Guo,Mingqiang,et al."A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration".IEEE Journal of Solid-State Circuits 55.3(2020):693-705.
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